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I get the whole OR1200 project from cvs.

I'm not aware of any documentation for the ORP stuff. Here is some
information about the TC module and its use in the ORP, I hope you
find it helpful.

If anyone sees any mistakes in here, please feel free to correct them,
it's been a while since I've used this stuff.

The tc_top.v module is the Traffic Cop and is basically responsible
for directing traffic on the Wishbone bus (not just a clever name,
eh?). It allows 8 Wishbone initiators (master s) and 9 Wishbone
targets (slaves). Arbitration for multiple initiator access is
performed based on Initiator priority (no round robin or anything like
that). Initiator 0 has highest priority and initiator 7 has the
lowest.

The TC actually has a separate data path for its 8 initiators to
access target 0, and another data path for the 8 initiators to access
targets 1 - 8. So even when target 0 is being accessed, targets 1-8
are still accessible.

In the case of the ORP, the VGA controller is connected to target 0
since it receives a high-level of traffic, I assume, and would
otherwise starve the Wishbone bus of cycles for other interesting
peripherals (such as memory or Ethernet).

In the ORP xsv_fpga_top.v module, the Wishbone bus addressing is as follows.

Target 0 0x00000000 - 0x00ffffff (16M)
Target 1 0x04000000 - 0x04ffffff (16M)
Target 2 0x97000000 - 0x97ffffff (16M)
Target 3 0x92000000 - 0x92ffffff (16M)
Target 4 0x9d000000 - 0x9dffffff (16M)
Target 5 0x90000000 - 0x9fffffff (16M)
Target 6 0x94000000 - 0x94ffffff (16M)
Target 7 0x9e000000 - 0x9effffff (16M)
Target 8 0x9f000000 - 0x9fffffff (16M)

On 4/13/05, tugen@c... <tugen@c...> wrote:
> I get the whole OR1200 project from cvs.
> 
> The xsv_fpga_top.v is top file. All IPs are connected in tc_top.v
> through WISHBONE. But this file is hard to understand to me. Is shared
> bus interconnection?
> 
> Have some documents introduce tc_top.v?
> 
> Eric Qiu
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
>