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Message
From: tugen@c...<tugen@c...>
Date: Wed Apr 13 18:58:59 CEST 2005
Subject: [openrisc] How to understand tc_top.v
I get the whole OR1200 project from cvs.The xsv_fpga_top.v is top file. All IPs are connected in tc_top.v
through WISHBONE. But this file is hard to understand to me. Is shared
bus interconnection?
Have some documents introduce tc_top.v?
Eric Qiu
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