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Message
From: vasant_mv@y...<vasant_mv@y...>
Date: Mon Apr 4 17:09:11 CEST 2005
Subject: [openrisc] problem with my code help needed
Sir
I am writing code for a simple RAM which is not working. Data is not
loading into the bidirectional data bus. I dont know where is the
mistake. Please kindly help me. My code is
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sram is
port(
clock: in std_logic;
enable: in std_logic;
rwbar: in std_logic; -- (1 - Read, 0 - Write)
addr: in std_logic_vector(4 downto 0);
data: inout std_logic_vector(15 downto 0)
);
end sram;
architecture sram_arch of sram is
type ram_type is array (0 to 31) of
std_logic_vector(15 downto 0);
signal tmp_ram: ram_type;
begin
process(clock)
begin
if(clock='1' and clock'event) then
if(enable='1') then
if(rwbar='1') then
data <= tmp_ram
(conv_integer(addr));
elsif(rwbar='0') then
tmp_ram(conv_integer
(addr)) <= data;
else
data <= (data'range
=> 'Z');
end if;
else
data <= (data'range => 'Z');
end if;
end if;
end process;
end sram_arch;
there is one more code i downloaded but not serving my purpose
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity mc8051_ramx is
port (clk : in std_logic; -- clock signal
data_bus : inout std_logic_vector(7 downto 0); -- data input
addr_bus : in std_logic_vector(4 downto 0); -- adresses
ram_wr_i : in std_logic; -- read=0, write=1
rst_b : in std_logic);
end mc8051_ramx;
architecture sim of mc8051_ramx is
type ram_type is array (31 downto 0) of bit_vector(7 downto 0);
begin
p_readwrite : process (clk, rst_b)
variable gpram: ram_type; -- general purpose RAM
begin
if rst_b='0' then
data_bus <= "00000000";
gpram := (others => (others =>'0')); -- rst_b every bit
else
if (clk'event and clk = '1' ) then
data_bus <= to_stdlogicvector(gpram(conv_integer(unsigned
(addr_bus))));
if ram_wr_i='1' then
gpram(conv_integer(unsigned(addr_bus))) := to_bitvector
(data_bus);
end if;
end if;
end if;
end process p_readwrite;
end sim;
Please kindly look through it
Vasant
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