LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Matjaz Breskvar<phoenix@o...>
    Date: Mon Mar 28 00:56:36 CEST 2005
    Subject: [openrisc] [or1ksim #33] Revamp the scheduler
    Top
    * György 'nog' Jeney (nog@s...) wrote:
    > Hi,
    >
    > This patch revamps the scheduler. This is needed so that I don't need to
    > compare 64-bits in the recompiler after each instruction. This is done by
    > storeing how many cycles are still outstanding to run the next job. The number
    > of outsanding cycles are stored as 32-bit numbers but a time-out of 2147483648
    > cycles is long enough.
    >
    > Since every single call to SCHED_ADD added a magic number to runtime.sim.cycles
    > I changed the interface to only require the time-out number (which just leads to
    > a simpler interface).
    >
    > I also changed the interface to a linked list implementation. In the old code
    > if you were running some number of peripherals the implementation reduced to
    > shift-all, which is simply put sub optimal.
    >
    > ChangeLog:
    > * Change scheduler to count down to 0 instead of reaching a certain cycle
    > count.
    > * Change the SCHED_ADD interface to take a time out as the parameter instead of
    > the number of cycles.

    accepted.

    > - SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
    > + SCHED_ADD( dma_channel_clock, channel, 1 );

    the only thing left to desire is configurable delay for
    each peripheral, but let's not go into details till we
    finish the integration...

    > - SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
    > + SCHED_ADD( dma_channel_clock, channel, dma_delay );

    best regards,
    p.

    ReferenceAuthor
    [openrisc] [or1ksim #33] Revamp the scheduler=?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.