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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Fri Mar 25 12:34:37 CET 2005
Subject: [openrisc] [or1ksim #39] Remove dc_clock
Hi,

This seems to have fallen through the cracks os I'm resubmiting it.

This removes the need for dc_clock. dc_clock only checked some sprs and did
some invalidateing/prefetching which has been moved into mtspr. This should
also speed up execution in the complex/simple models aswell.

ChangeLog:
* Do what dc_clock() did in mtspr() and remove it.

nog.
-------------- next part --------------
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/cache/dcache_model.c ./cache/dcache_model.c
--- /home/nog/or1ksim-split/cache/dcache_model.c 2005-03-21 20:08:39.000000000 +0100
+++ ./cache/dcache_model.c 2005-03-16 12:39:36.000000000 +0100
@@ -322,30 +322,6 @@ void dc_inv(oraddr_t dataaddr)
}
}

-void dc_clock()
-{
- oraddr_t addr;
-
- if ((addr = mfspr(SPR_DCBPR))) {
- dc_simulate_read(addr, 4);
- mtspr(SPR_DCBPR, 0);
- }
- if ((addr = mfspr(SPR_DCBFR)) != -1) {
- dc_inv(addr);
- mtspr(SPR_DCBFR, -1);
- }
- if ((addr = mfspr(SPR_DCBIR))) {
- dc_inv(addr);
- mtspr(SPR_DCBIR, 0);
- }
- if ((addr = mfspr(SPR_DCBWR))) {
- mtspr(SPR_DCBWR, 0);
- }
- if ((addr = mfspr(SPR_DCBLR))) {
- mtspr(SPR_DCBLR, 0);
- }
-}
-
/*-----------------------------------------------------[ DC configuration ]---*/
void dc_enabled(union param_val val, void *dat)
{
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/cache/dcache_model.h ./cache/dcache_model.h
--- /home/nog/or1ksim-split/cache/dcache_model.h 2005-03-16 12:36:30.000000000 +0100
+++ ./cache/dcache_model.h 2005-03-16 12:39:36.000000000 +0100
@@ -24,4 +24,4 @@
uint32_t dc_simulate_read(oraddr_t dataaddr, int width);
void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width);
void dc_info();
-void dc_clock();
+void dc_inv(oraddr_t dataaddr);
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/toplevel.c ./toplevel.c
--- /home/nog/or1ksim-split/toplevel.c 2005-03-22 16:57:30.000000000 +0100
+++ ./toplevel.c 2005-03-21 19:28:40.000000000 +0100
@@ -425,7 +425,6 @@ int main(argc, argv)
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;
if (cpu_clock ()) break;
- if (config.dc.enabled) dc_clock();
if (config.ic.enabled) ic_clock();
}

--- cpu/or1k/sprs.c 2005-03-21 20:08:39.000000000 +0100
+++ /home/nog/or1ksim-split/cpu/or1k/sprs.c 2005-03-22 17:20:09.000000000 +0100
@@ -35,6 +35,7 @@
#include "sim-config.h"
#include "except.h"
#include "execute.h"
+#include "dcache_model.h"

extern int flag;

@@ -58,6 +59,31 @@
case SPR_TTMR:
spr_write_ttmr (value);
break;
+ /* Data cache simulateing stuff */
+ case SPR_DCBPR:
+ if(value) {
+ dc_simulate_read(value, 4);
+ sprs[SPR_DCBPR] = 0;
+ }
+ break;
+ case SPR_DCBFR:
+ if(value != -1) {
+ dc_inv(value);
+ sprs[SPR_DCBFR] = -1;
+ }
+ break;
+ case SPR_DCBIR:
+ if(value != 0) {
+ dc_inv(value);
+ sprs[SPR_DCBIR] = 0;
+ }
+ break;
+ case SPR_DCBWR:
+ sprs[SPR_DCBWR] = 0;
+ break;
+ case SPR_DCBLR:
+ sprs[SPR_DCBLR] = 0; + break; case SPR_SR: /* Set internal flag also */ if(value & SPR_SR_F) flag = 1;