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From: psungil@n...<psungil@n...>
Date: Fri Mar 25 03:54:18 CET 2005
Subject: [openrisc] mc_ctrl's clock and cs
Hello~,

I just attetching mc_ctrl(memory controller) and flash I/F at wishibone
bus.
mc_ctrl has adress area : 0x0000_0000 ~
flash is : 0x2000_0000 ~
so, mc_ctrl ' s memory : SDRAM (PC100)

My wishbone bus clock is 50Mhz and SDRAM 25Mhz...
there are different clocks.

I try to debugging with jtag, but it not working.
It seems to be reset or clock Freq. problems.

how to wired between wishbone bus and mc_ctrl ?