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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Thu Mar 24 21:09:40 CET 2005
Subject: [openrisc] [or1ksim #47] Rearange some code in the immu
Hi,

This those the same for the immu that #45 did for the dmmu for the same reasons.

ChangeLog:
* Rearange some code such that it is not assumed that except_handle returns.

nog.
-------------- next part --------------
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/mmu/immu.c ./mmu/immu.c
--- /home/nog/or1ksim-split/mmu/immu.c 2005-03-22 18:37:39.000000000 +0100
+++ ./mmu/immu.c 2005-03-16 12:39:36.000000000 +0100
@@ -72,15 +72,6 @@ static inline oraddr_t immu_simulate_tlb
immu_stats.fetch_tlbhit++;
TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);

- /* Test for page fault */
- if (mfspr (SPR_SR) & SPR_SR_SM) {
- if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
- except_handle(EXCEPT_IPF, virtaddr);
- } else {
- if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
- except_handle(EXCEPT_IPF, virtaddr);
- }
-
/* Set LRUs */
for (i = 0; i < config.immu.nways; i++)
if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
@@ -91,6 +82,16 @@ static inline oraddr_t immu_simulate_tlb
insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;

runtime.sim.mem_cycles += config.immu.hitdelay;
+
+ /* Test for page fault */
+ if (mfspr (SPR_SR) & SPR_SR_SM) {
+ if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
+ except_handle(EXCEPT_IPF, virtaddr);
+ } else {
+ if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
+ except_handle(EXCEPT_IPF, virtaddr);
+ }
+
ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
}
@@ -109,10 +110,12 @@ static inline oraddr_t immu_simulate_tlb
setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
#endif
- except_handle(EXCEPT_ITLBMISS, virtaddr);
+
/* if tlb refill implemented in HW */
/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
runtime.sim.mem_cycles += config.immu.missdelay;
+
+ except_handle(EXCEPT_ITLBMISS, virtaddr);
return 0;
}
}