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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Thu Mar 24 21:09:27 CET 2005
Subject: [openrisc] [or1ksim #45] Rearange code in the dmmu
Hi,

In the dynamic recompiler except_handle does not return hence if an DTLB miss or
a DPF occured some vital code never ended up being executed. This fixes it.

ChangeLog:
* Rearange code in the dmmu such that it is not assumed that except_handle
returns.

nog.
-------------- next part --------------
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/mmu/dmmu.c ./mmu/dmmu.c
--- /home/nog/or1ksim-split/mmu/dmmu.c 2005-03-22 18:31:28.000000000 +0100
+++ ./mmu/dmmu.c 2005-03-16 12:39:36.000000000 +0100
@@ -71,17 +73,6 @@ inline oraddr_t dmmu_simulate_tlb(oraddr
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
runtime.sim.cycles);

- /* Test for page fault */
- if (mfspr (SPR_SR) & SPR_SR_SM) {
- if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
- || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
- except_handle(EXCEPT_DPF, virtaddr);
- } else {
- if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
- || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
- except_handle(EXCEPT_DPF, virtaddr);
- }
-
/* Set LRUs */
for (i = 0; i < config.dmmu.nways; i++)
if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
@@ -93,6 +84,18 @@ inline oraddr_t dmmu_simulate_tlb(oraddr

runtime.sim.mem_cycles += config.dmmu.hitdelay;
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
+
+ /* Test for page fault */
+ if (mfspr (SPR_SR) & SPR_SR_SM) {
+ if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
+ || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
+ except_handle(EXCEPT_DPF, virtaddr);
+ } else {
+ if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
+ || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
+ except_handle(EXCEPT_DPF, virtaddr);
+ }
+
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
}
else { /* No, we didn't. */
@@ -110,12 +113,12 @@ inline oraddr_t dmmu_simulate_tlb(oraddr
setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
#endif
- except_handle(EXCEPT_DTLBMISS, virtaddr);
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
runtime.sim.cycles);
+ runtime.sim.mem_cycles += config.dmmu.missdelay;
/* if tlb refill implemented in HW */
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
- runtime.sim.mem_cycles += config.dmmu.missdelay;
+ except_handle(EXCEPT_DTLBMISS, virtaddr);
return 0;
}
}