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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Thu Mar 24 21:09:00 CET 2005
Subject: [openrisc] [or1ksim #40] Remove the need for ic_clock()
Hi,

This does the same with the instruction cache that #39 did for the data cache.

ChangeLog:
* Move the function of ic_clock() to mtspr() and remove it.

nog.
-------------- next part --------------
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/cache/icache_model.c ./cache/icache_model.c
--- cache/icache_model.c 2005-03-21 20:08:39.000000000 +0100
+++ ./cache/icache_model.c 2005-03-16 12:39:36.000000000 +0100
@@ -196,23 +196,6 @@
}
}

-void ic_clock()
-{
- oraddr_t addr;
-
- if ((addr = mfspr(SPR_ICBPR))) {
- ic_simulate_fetch(addr);
- mtspr(SPR_ICBPR, 0);
- }
- if ((addr = mfspr(SPR_ICBIR))) {
- ic_inv(addr);
- mtspr(SPR_ICBIR, 0);
- }
- if ((addr = mfspr(SPR_ICBLR))) {
- mtspr(SPR_ICBLR, 0);
- }
-}
-
/*-----------------------------------------------------[ IC configuration ]---*/
void ic_enabled(union param_val val, void *dat)
{
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/cache/icache_model.h ./cache/icache_model.h
--- /home/nog/or1ksim-split/cache/icache_model.h 2005-03-16 12:36:30.000000000 +0100
+++ ./cache/icache_model.h 2005-03-16 12:39:36.000000000 +0100
@@ -22,5 +22,5 @@
#define MAX_IC_BLOCK_SIZE 4 /* In words */

uint32_t ic_simulate_fetch(oraddr_t fetchaddr);
+void ic_inv(oraddr_t dataaddr);
void ic_info();
-void ic_clock();
diff -urp --unidirectional-new-file /home/nog/or1ksim-split/cpu/or1k/sprs.c ./cpu/or1k/sprs.c
--- cpu/or1k/sprs.c 2005-03-22 17:22:54.000000000 +0100
+++ ./cpu/or1k/sprs.c 2005-03-21 18:24:55.000000000 +0100
@@ -36,6 +36,7 @@
#include "except.h"
#include "execute.h"
#include "dcache_model.h"
+#include "icache_model.h"

extern int flag;

@@ -83,6 +84,22 @@
break;
case SPR_DCBLR:
sprs[SPR_DCBLR] = 0;
+ break;
+ /* Instruction cache simulateing stuff */
+ case SPR_ICBPR:
+ if(value) {
+ ic_simulate_fetch(value);
+ sprs[SPR_ICBPR] = 0;
+ }
+ break;
+ case SPR_ICBIR:
+ if(value) {
+ ic_inv(value);
+ sprs[SPR_ICBIR] = 0;
+ }
+ break;
+ case SPR_ICBLR:
+ sprs[SPR_ICBLR] = 0;
break;
case SPR_SR:
/* Set internal flag also */
--- /home/nog/or1ksim-split/toplevel.c 2005-03-22 17:22:54.000000000 +0100
+++ ./toplevel.c 2005-03-21 19:28:40.000000000 +0100
@@ -425,7 +425,6 @@
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;
if (cpu_clock ()) break;
- if (config.ic.enabled) ic_clock();
}

if (config.vapi.enabled && runtime.vapi.enabled) vapi_check();