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Message
From: Matjaz Breskvar<phoenix@o...>
Date: Sat Feb 19 01:54:51 CET 2005
Subject: [openrisc] instruction cache
Ok, i should have removed some code from this two functions.
it's commented out in this email...
best regards,
p.
* Matjaz Breskvar (phoenix@o...) wrote:
> * sankar@m... (sankar@m...) wrote:
>
> Hi,
>
> > Could you give a software example (preferrably in assembly) which
> > does that?
>
> This is from Linux...
>
> The define names may or may not be obvious to you... if
> they are not please ask again... ;)
>
>
> # define ENTRY(symbol) \
> .global symbol ;\
> symbol:
>
>
> ENTRY(_ic_enable)
/*
* SF_DISABLED(r6,INIT_IC_ADDR)
* l.bf 9f
* l.nop
*/
> /* Disable IC */
> l.mfspr r6,r0,SPR_SR
> l.addi r5,r0,-1
> l.xori r5,r5,SPR_SR_ICE
> l.and r5,r6,r5
> l.mtspr r0,r5,SPR_SR
>
> /* Invalidate IC */
> l.addi r6,r0,0
> l.addi r5,r0,IC_SIZE
> 1:
> l.mtspr r0,r6,SPR_ICBIR
> l.sfne r6,r5
> l.bf 1b
> l.addi r6,r6,IC_LINE
>
> /* Enable IC */
> l.mfspr r6,r0,SPR_SR
> l.ori r6,r6,SPR_SR_ICE
> l.mtspr r0,r6,SPR_SR
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> l.nop
> 9:
> l.jr r9
> l.nop
>
>
> ENTRY(_dc_enable)
/*
* SF_DISABLED(r6,INIT_DC_ADDR)
* l.bf 9f
* l.nop
*/
> /* Disable DC */
> l.mfspr r6,r0,SPR_SR
> l.addi r5,r0,-1
> l.xori r5,r5,SPR_SR_DCE
> l.and r5,r6,r5
> l.mtspr r0,r5,SPR_SR
>
> /* Flush DC */
> l.addi r6,r0,0
> l.addi r5,r0,DC_SIZE
> 1:
> l.mtspr r0,r6,SPR_DCBIR
> l.sfne r6,r5
> l.bf 1b
> l.addi r6,r6,DC_LINE
>
> /* Enable DC */
> l.mfspr r6,r0,SPR_SR
> l.ori r6,r6,SPR_SR_DCE
> l.mtspr r0,r6,SPR_SR
> 9:
> l.jr r9
> l.nop
>
>
> > I am asking this because I thought while using or32-uclinux tools
> > to compile my assembly with cache that is automatically done. I have
> > included the Makefile below.
>
> or32-uclinux tools do not automaticaly clear the cache. the code
> in the source file has to do it explicitly...
>
> best regards,
> p.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
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