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* jcastillo (jcastillo@o...) wrote:

Hello,
  Could you give a software example (preferrably in assembly) which
does that?
   I am asking this because I thought while using or32-uclinux tools
to compile my assembly with cache that is automatically done. I have
included the Makefile below.
*************************************
all: test-icdc

test-icdc: test.o ../support/reset-icdc.o
        or32-uclinux-ld -T ../support/orp.ld $? -o $@.or32
./support/libsupport.a
        or32-uclinux-objcopy -O binary $@.or32 $@.bin
        ../utils/bin2hex $@.bin > $@.hex
        cp $@.hex ../../sim/src/

test.o: test.S
        or32-uclinux-gcc -O0 $? -c -o $@

clean:
        rm -f *.o *.or32 *.log *.bin *.hex
******************************************
 Could you tell me what the problem is?
Thanks,
Sankar

----- Original Message ----- 
From: Matjaz Breskvar<phoenix@o...> 
To: 
Date: Wed Feb 16 01:36:52 CET 2005 
Subject: [openrisc] instruction cache 

> * jcastillo (jcastillo@o...) wrote: 
> 
> Also, don't forget to clear the cache before you enable it... 
> 
> best regards, 
> p. 
> > You have to write in the SR the bits which enables the cache 
> operation. This 
> > operation has to be done by the software. 
> > 
> > Regards 
> > 
> > Javier Castillo 
> > jcastillo@o... 
> > 
> > 
> > -----Mensaje original----- 
> > De: openrisc-bounces@o... 
> [mailto:openrisc-bounces@o...] 
> > En nombre de sankar@m... 
> > Enviado el: sábado, 12 de febrero de 2005 0:54 
> > Para: openrisc@o... 
> > Asunto: [openrisc] instruction cache 
> > 
> > Hi all, 
> > I want to use the OR1200 with instruction cache. So I 
> commented the 
> > OR1200_NO_IC in the defines file and uncommented the 
> OR1200_IC_1W_8KB 
> > defines. But still 'ic_en' signal was not getting enabled. If 
> I try to 
> > enable it by hardwiring the assigning of ic_en then it starts 
> reading 
> > garbage (all 'x' s) from the cache and causes abnormal 
> function. So 
> > what is the correct way to enable instruction cache? 
> > 
> > Thanks, 
> > Sankar 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/openrisc 
> > 
> > 
> > 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/openrisc 
> 
> 