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From: jcastillo<jcastillo@o...>
Date: Mon Feb 14 11:27:00 CET 2005
Subject: [openrisc] instruction cache
You have to write in the SR the bits which enables the cache operation. This
operation has to be done by the software.

Regards

Javier Castillo
jcastillo@o...


-----Mensaje original-----
De: openrisc-bounces@o... [mailto:openrisc-bounces@o...]
En nombre de sankar@m...
Enviado el: sábado, 12 de febrero de 2005 0:54
Para: openrisc@o...
Asunto: [openrisc] instruction cache

Hi all,
I want to use the OR1200 with instruction cache. So I commented the
OR1200_NO_IC in the defines file and uncommented the OR1200_IC_1W_8KB
defines. But still 'ic_en' signal was not getting enabled. If I try to
enable it by hardwiring the assigning of ic_en then it starts reading
garbage (all 'x' s) from the cache and causes abnormal function. So
what is the correct way to enable instruction cache?

Thanks,
Sankar
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Follow up	Author
[openrisc] instruction cache	Matjaz Breskvar