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From: patrik.thalin@s...<patrik.thalin@s...>
Date: Sun Jan 30 14:27:17 CET 2005
Subject: [openrisc] Whisbone cycle in openrisc core
Hi,

According to the specifications there can be any number of wait states
in a whisbone read/write cycle. But when I simulate the openrisc core
it seem to fail if there are more that two clock cycles. I get an X
driving the cyc_i and std_i if the ack_o is set later that two clock
cycles after cyc_i is set.

The problem is that i need a cycle longer that that.

Any ideas?

/Patrik