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Check the verilog file list and directory related UART.

You indeed do need a change. For some reason, a few files were missing
in  the verilog file list. (Compare with the directory checked out).
You need to include them to run the simulation.

Thanks,

Farhan

----- Original Message ----- 
From: Kyeong Bong Ha<kyeongbong.ha@g...> 
To: 
Date: Thu Jan 27 01:10:19 CET 2005 
Subject: [openrisc] RTL simulation 

> Check the verilog file list and directory related UART. 
> Maybe, you need some change. 
> On Wed, 26 Jan 2005 00:56:00 +0100, sonatomy@y... 
> <sonatomy@y...> wrote: 
> > Dear Sir, 
> > 
> > I am trying to run RTL simulation using the run_rtl_regression 
> script 
> > in NCVerilog. 
> > I have compiled and built the sw testcases using the run-sw 
> script. 
> > It is giving me a translation error as follows (ncprep error). 
> > 
> > ncvlog: *E,NOBIND: no rule to search for instance 
> > 'i_uart_sync_flops::uart_sync_flops'. 
> > Total errors/warnings found outside modules and primitives: 
> > errors: 1, warnings: 0 
> > ncprep: *E,VLGERR: Error during parsing (status 1), exiting. 
> > Translation Failed! 
> > 
> > Has anyone come across this error? 
> > Is it due to wrong version being checked out of the cvs? 
> > Iam running this on a solaris machine. Could that be a reason 
> for it 
> > not generating the required bind.lst file? 
> > Any help is very much appreciated. 
> > Thanks in advance 
> > Sona 
> > 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/openrisc 
> > 
> 
> 