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Message
From: Damon Brantley<brantley@m...>
Date: Sat Jan 22 05:35:17 CET 2005
Subject: [openrisc] OR32/uclinux for webpack
I have created a webpack project to build the openrisc cpu and additional
peripherals for the Xess XSA-3S1000 board.
Balint Cristian has offered to make a zipped version of the project
available for download at http://openrisc.rdsor.ro/socterm.tar.gz
The project includes the following:
OR32 from opencores
UART from opencores
sdram controller written by me(not elegant, but it works)
a simple dumb terminal using T80 cpu with 8K blockram
ps2 controller from opencores
jtag debug interface. I have successfully interfaced this using a modified
version of jp2 that has all the 8051 stuff removed.
Miscellaneous other bits and pieces.
Also included are various test programs written in c.
The gcc build environment is not included.
Files of interest.
xilinx/soc/soctop.bit Prebuilt fpga file
c/memtest/tmp/memtest.xes Memory test program for sdram
c/linux/tmp/linux.xes uclinux
Use gsxload for the above files.
The dumb terminal does not decode keystrokes or terminal control
characters. So the display
will look a little funny, but it is enough to see what is going on.
This not meant to be complete project. This is only meant to help others
who are just getting started with the XSA-3S1000 board to get a head start
if they want to use OR32 with the webpack.
I do not consider the project suitable for inclusion into CVS because
webpack/modelsim does not handle having project files
located in multiple directories. Also some modifications to or32 files were
made to make things build in webpack and work properly in modelsim.
One other note. In the soctop.v file there is a define called SIM. This
will switch the sdram memory model in/out for simulation purposes.
Enjoy
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