LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Balint Cristian<rezso@r...>
    Date: Sat Jan 15 15:37:12 CET 2005
    Subject: [openrisc] An advice
    Top
    On Saturday 15 January 2005 15:51, brantley@m... wrote:


    Hi Brantley !

    I possess an XSA-3S1000 too, unfortunatley i wasnt able to go so far than compile
    the project for this board. Can please help me with the main project files of [i guess ISE 6.x or Sympl] ?

    Would be nice if publish somewhere the project [even in that stage] for this new XSA-3S1000 board,
    i think there would be high interest of others, especialy that the the board is really cheap and the XVS800
    one board is obsloeted.

    Myself I would love if share it with me.


    ~cristian


    > I have been working with the XSA-3S1000 for the last several weeks. I
    > have been having a lot of problems trying to get uclinux to come up on
    > openrisc. Other test programs I have written have been stable. It
    > seems to be related to timing constraints. Maybe because the place
    > and route has too much space to put things. I did finally get a boot
    > to a shell prompt, but only after I had almost 97% utilization from
    > adding in an onboard serial terminal and the or1k debug/jtag. I also
    > have the constraints for MAXDELAY and MAXSKEW set to 1ns for the or1k
    > and sdram connections to tctop. Place and route effort is set to
    > hight. I am not sure if these are really where the constraints need to
    > be set, but it is booting up. Currently I am running the or1k at 25Mhz
    > and the sdram controller at 100Mhz.
    >
    > ----- Original Message -----
    > From: Giacomo Bernardi<bernardi.giacomo@t...>
    > To:
    > Date: Wed Jan 12 16:16:56 CET 2005
    > Subject: [openrisc] An advice
    >
    > > I'm planning to buy XSA-3S1000 for synthesizing openrisc-1100 ( or
    > > 1200 ) and
    > > do some experience. Are there any contraddiction ( like that the
    > > external
    > > memory on board is only 16 bit adressable ) ?
    > > If not, is there anyone that knows what area occupation it have in
    > > that
    > > FPGA?
    > > And wich clock frequency is obtainable?
    > > For implementing openrisc is better a Spartan FPGA, a Virtex2 or is
    > > it
    > > indifferent ( beetween the Xilinx architectures ) ?
    > > Thanks in advance.
    > > Regards Giacomo
    > >
    > >
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/openrisc
    >

    ReferenceAuthor
    [openrisc] An adviceBrantley

    Follow upAuthor
    [openrisc] An adviceDamon Brantley

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.