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Message
From: brantley@m...<brantley@m...>
Date: Sat Jan 15 14:51:30 CET 2005
Subject: [openrisc] An advice
I have been working with the XSA-3S1000 for the last several weeks. I
have been having a lot of problems trying to get uclinux to come up on
openrisc. Other test programs I have written have been stable. It
seems to be related to timing constraints. Maybe because the place
and route has too much space to put things. I did finally get a boot
to a shell prompt, but only after I had almost 97% utilization from
adding in an onboard serial terminal and the or1k debug/jtag. I also
have the constraints for MAXDELAY and MAXSKEW set to 1ns for the or1k
and sdram connections to tctop. Place and route effort is set to
hight. I am not sure if these are really where the constraints need to
be set, but it is booting up. Currently I am running the or1k at 25Mhz
and the sdram controller at 100Mhz.
----- Original Message -----
From: Giacomo Bernardi<bernardi.giacomo@t...>
To:
Date: Wed Jan 12 16:16:56 CET 2005
Subject: [openrisc] An advice
> I'm planning to buy XSA-3S1000 for synthesizing openrisc-1100 ( or
> 1200 ) and
> do some experience. Are there any contraddiction ( like that the
> external
> memory on board is only 16 bit adressable ) ?
> If not, is there anyone that knows what area occupation it have in
> that
> FPGA?
> And wich clock frequency is obtainable?
> For implementing openrisc is better a Spartan FPGA, a Virtex2 or is
> it
> indifferent ( beetween the Xilinx architectures ) ?
> Thanks in advance.
> Regards Giacomo
>
>
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