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>Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx

Dear sir,
Thanks very much for the help.
I tried with expansion header pins , similar to the ones in the ucf file 
uploaded under rc203. I used the fpga general i/o pinouts m2,n2,p2,m4 
(TCK,TDI,TDO,TMS) which is connected to the expansion header.
I used one of the buttons to trst signal.
Iam getting the error message saying
reset()
"crc failed"

Will it be my communication problem or some problem in my design?
Thanks and best regards
Sona

----- Original Message ----- 
From: jcastillo<jcastillo@o...> 
To: 
Date: Thu Jan 13 12:08:02 CET 2005 
Subject: [openrisc] ORPSoC JTAG pin assignment 

> >Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx 
> spartan3 
> >Parallel port JTAG cable which we modified with flying leads to 
> fit to 
> >RC200 board to establish the communication. The modified cable 
> works 
> >fine with the Xilinx impact and detects the JTAG chain.What 
> implications 
> >can this have on my design not working? 
> >Really would appreciate any sort of help ASAP........... 
> >Thanks in advance for your support... 
> >Best Regards 
> >Sona 
> The ucf files are prepared to connect the parallel cable to the 
> expansion 
> header, take a look to it to see how to connect them. 
> To program the FPGA use the FTU program provided by Celoxica or 
use 
> another 
> JTAG cable connected to the JTAG header to program the FPGA. 
> Best Regards 
> Javier Castillo 
> jcastillo@o... 
> _______________________________________________ 
> http://www.opencores.org/mailman/listinfo/openrisc 
> 
> 