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From: Igor Mohor<igor.mohor@g...>
Date: Thu Jan 13 12:29:24 CET 2005
Subject: [openrisc] ORPSoC JTAG pin assignment
Of course you got the DRC errors.

TCK, TDI, TDO and TMS are reserved pins (used when internal JTAG is used).
You need to take any other (general purpose in/out pins).

Regards,
Igor


On Wed, 12 Jan 2005 20:53:12 +0100, sonatomy@y...
<sonatomy@y...> wrote:
> Dear Sir,
>
> I have followed the instructions of Basic Custom ORPSoC HW tutorial
> and software tutorial.I have been trying to communicate with my design
> on board through the parallel port and jp1 server. It has failed.
> Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the
> pin assignments for the jtag pins of the ORPSoC design?
>
> I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20
> (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE.
>
> Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3
> Parallel port JTAG cable which we modified with flying leads to fit to
> RC200 board to establish the communication. The modified cable works
> fine with the Xilinx impact and detects the JTAG chain.What implications
> can this have on my design not working?
>
> Really would appreciate any sort of help ASAP...........
> Thanks in advance for your support...
> Best Regards
> Sona
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