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Message
From: jcastillo<jcastillo@o...>
Date: Thu Jan 13 12:08:02 CET 2005
Subject: [openrisc] ORPSoC JTAG pin assignment
>Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3
>Parallel port JTAG cable which we modified with flying leads to fit to
>RC200 board to establish the communication. The modified cable works
>fine with the Xilinx impact and detects the JTAG chain.What implications
>can this have on my design not working?
>Really would appreciate any sort of help ASAP...........
>Thanks in advance for your support...
>Best Regards
>Sona
The ucf files are prepared to connect the parallel cable to the expansion
header, take a look to it to see how to connect them.
To program the FPGA use the FTU program provided by Celoxica or use another
JTAG cable connected to the JTAG header to program the FPGA.
Best Regards
Javier Castillo
jcastillo@o...
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