OPENCORES.ORG

Hi,

You can "disable" MMU and Caches prior to synthesis, so you will not have 
them in the implemented version. Likewise you can "disable" other units, and 
even some instructions (like division instructions, rorate, mac etc etc). 
This should make OR1200 about the same size as ARM7...

regards,
Damjan

----- Original Message ----- 
From: <stefano.lorenzini1@t...>
To: <openrisc@o...>
Sent: Monday, December 20, 2004 2:05 PM
Subject: [openrisc] ARM7 vs OpenRisc

> Hi,
>
> I'm looking for a replacement of an AMR7 processor, I was
> really impressed by the OpenRisc 1000 processor but it looks
> quite bugger since it has MMU and Caches capability
> that I don't neet.
>
> So, is someone able to suggest me a solution to replace my ARM
> with an "open" solution? Is there any way to use the OpenRisc1000
> in a dummy mode, meaning for example the possibility to exclude
> MMU and cache from the RTL code?
>
> Any gate counts figure about  OpenRisc1000, as such, would
> be available also.
>
> Thanks in advance for your advises.
>
> Best Regards
> Stefano
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
> 