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Message
From: stefano.lorenzini1@t...<stefano.lorenzini1@t...>
Date: Mon Dec 20 14:05:36 CET 2004
Subject: [openrisc] ARM7 vs OpenRisc
Hi,I'm looking for a replacement of an AMR7 processor, I was
really impressed by the OpenRisc 1000 processor but it looks
quite bugger since it has MMU and Caches capability
that I don't neet.
So, is someone able to suggest me a solution to replace my ARM
with an "open" solution? Is there any way to use the OpenRisc1000
in a dummy mode, meaning for example the possibility to exclude
MMU and cache from the RTL code?
Any gate counts figure about OpenRisc1000, as such, would
be available also.
Thanks in advance for your advises.
Best Regards
Stefano
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