|
Message
From: Matjaz Breskvar<phoenix@o...>
Date: Thu Aug 12 14:46:24 CEST 2004
Subject: [openrisc] GCC: support for l.cmov
* Vsevolod Lobko (seva@s...) wrote:
> On Mon, Aug 09, 2004 at 09:22:40PM +0200, Matjaz Breskvar wrote:
> > * Vsevolod Lobko (seva@s...) wrote:
> > > Hello,
> > >
> > > What happened with this patches?
> >
> > They is some problem with it, it fails to compile linux. I'm working
> > with Phill to fix it, but it seams we both have other priorities.
> >
> > if somebody wants to take a look at it in the meantime even better.
>
> Can you send me this patchset? I'll try to look at it...
ok, here you have it...
regards,
p.
-------------- next part --------------
Index: or1k/gcc-3.2.3/gcc/config/or32/or32-protos.h
diff -c or1k/gcc-3.2.3/gcc/config/or32/or32-protos.h:1.1.1.1 or1k/gcc-3.2.3/gcc/config/or32/or32-protos.h:1.2
*** or1k/gcc-3.2.3/gcc/config/or32/or32-protos.h:1.1.1.1 Wed Jul 7 00:23:34 2004
--- or1k/gcc-3.2.3/gcc/config/or32/or32-protos.h Mon Jul 12 14:10:11 2004
***************
*** 26,31 ****
--- 26,33 ----
extern void print_operand_address PARAMS ((FILE *, register rtx));
extern const char *or1k_output_move_double PARAMS ((rtx *operands));
+ extern rtx or1k_cmp_op[];
+
#endif /* RTX_CODE */
#ifdef TREE_CODE
Index: or1k/gcc-3.2.3/gcc/config/or32/or32.S
diff -c or1k/gcc-3.2.3/gcc/config/or32/or32.S:1.1.1.1 or1k/gcc-3.2.3/gcc/config/or32/or32.S:1.2
*** or1k/gcc-3.2.3/gcc/config/or32/or32.S:1.1.1.1 Wed Jul 7 00:23:34 2004
--- or1k/gcc-3.2.3/gcc/config/or32/or32.S Thu Jul 8 22:26:05 2004
***************
*** 112,124 ****
l.sw 4(r1),r10
l.addi r5,r3,0
l.addi r10,r0,0
! l.sflts r5,r10
l.bnf 1f
l.addi r3,r0,0
l.addi r10,r0,1
l.sub r5,r0,r5
1:
! l.sflts r4,r3
l.bnf 1f
l.nop 0
l.addi r10,r10,1
--- 112,124 ----
l.sw 4(r1),r10
l.addi r5,r3,0
l.addi r10,r0,0
! l.sflts r5,r0
l.bnf 1f
l.addi r3,r0,0
l.addi r10,r0,1
l.sub r5,r0,r5
1:
! l.sflts r4,r0
l.bnf 1f
l.nop 0
l.addi r10,r10,1
***************
*** 126,133 ****
1:
l.jal ___udivsi3
l.addi r3,r5,0
! l.addi r3,r0,1
! l.sfeq r10,r3
l.bnf 1f
l.nop 0
l.sub r11,r0,r11
--- 126,132 ----
1:
l.jal ___udivsi3
l.addi r3,r5,0
! l.sfeqi r10,1
l.bnf 1f
l.nop 0
l.sub r11,r0,r11
***************
*** 157,162 ****
--- 156,162 ----
l.addi r1,r1,-8
l.sw 0(r1),r9
l.sw 4(r1),r10
+ l.addi r10,r0,0
l.sflts r3,r0
l.bnf 1f
l.nop 0
***************
*** 170,177 ****
1:
l.jal ___udivsi3
l.nop 0
! l.addi r3,r0,1
! l.sfeq r10,r3
l.bnf 1f
l.addi r11,r7,0
l.sub r11,r0,r11
--- 170,176 ----
1:
l.jal ___udivsi3
l.nop 0
! l.sfeqi r10,1
l.bnf 1f
l.addi r11,r7,0
l.sub r11,r0,r11
***************
*** 180,183 ****
l.lwz r10,4(r1)
l.jr r9
l.addi r1,r1,8
! #endif
\ No newline at end of file
--- 179,182 ----
l.lwz r10,4(r1)
l.jr r9
l.addi r1,r1,8
! #endif
Index: or1k/gcc-3.2.3/gcc/config/or32/or32.c
diff -c or1k/gcc-3.2.3/gcc/config/or32/or32.c:1.1.1.1 or1k/gcc-3.2.3/gcc/config/or32/or32.c:1.2
*** or1k/gcc-3.2.3/gcc/config/or32/or32.c:1.1.1.1 Wed Jul 7 00:23:34 2004
--- or1k/gcc-3.2.3/gcc/config/or32/or32.c Mon Jul 12 14:10:11 2004
***************
*** 38,43 ****
--- 38,45 ----
of l.jr instruction in epilogue. */
#define NOP_DELAY_SLOT_FILL 0
+ rtx or1k_cmp_op[2];
+
/* used in function prologue/epilogue generation */
extern int leaf_function;
Index: or1k/gcc-3.2.3/gcc/config/or32/or32.h
diff -c or1k/gcc-3.2.3/gcc/config/or32/or32.h:1.1.1.1 or1k/gcc-3.2.3/gcc/config/or32/or32.h:1.3
*** or1k/gcc-3.2.3/gcc/config/or32/or32.h:1.1.1.1 Wed Jul 7 00:23:34 2004
--- or1k/gcc-3.2.3/gcc/config/or32/or32.h Wed Jul 14 13:09:26 2004
***************
*** 62,73 ****
{"soft-div", - MASK_HARD_DIV, N_("Use software divison.")}, \
{"hard-mul", MASK_HARD_MUL, N_("Use hardware multiplication.")}, \
{"soft-mul", - MASK_HARD_MUL, N_("Use software multiplication.")}, \
! { "", TARGET_DEFAULT, 0x00000004}}
/* Default target_flags if no switches specified. */
#ifndef TARGET_DEFAULT
! #define TARGET_DEFAULT (0x00000004)
#endif
/* Target machine storage layout */
--- 62,73 ----
{"soft-div", - MASK_HARD_DIV, N_("Use software divison.")}, \
{"hard-mul", MASK_HARD_MUL, N_("Use hardware multiplication.")}, \
{"soft-mul", - MASK_HARD_MUL, N_("Use software multiplication.")}, \
! { "", TARGET_DEFAULT, 0}}
/* Default target_flags if no switches specified. */
#ifndef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_HARD_MUL)
#endif
/* Target machine storage layout */
***************
*** 216,222 ****
and are not available for the register allocator.
On the or1k, these are r1 as stack pointer and
r2 as frame/arg pointer. */
! #define FIXED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
--- 216,222 ----
and are not available for the register allocator.
On the or1k, these are r1 as stack pointer and
r2 as frame/arg pointer. */
! #define FIXED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 \
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
Index: or1k/gcc-3.2.3/gcc/config/or32/or32.md
diff -c or1k/gcc-3.2.3/gcc/config/or32/or32.md:1.1.1.1 or1k/gcc-3.2.3/gcc/config/or32/or32.md:1.9
*** or1k/gcc-3.2.3/gcc/config/or32/or32.md:1.1.1.1 Wed Jul 7 00:23:34 2004
--- or1k/gcc-3.2.3/gcc/config/or32/or32.md Sun Aug 1 15:40:17 2004
***************
*** 122,204 ****
;;
! ;; Conditional Branches
;;
! (define_expand "cbranchsi4"
! [(set (pc) (if_then_else
! (match_operator 0 "comparison_operator"
! [(match_operand:SI 1 "register_operand" "r,r")
! (match_operand:SI 2 "nonmemory_operand" "r,I")])
! (label_ref (match_operand 3 "" ""))
! (pc)))]
! ""
! "
! {
! int compare_code = GET_CODE (operands[0]);
!
! if (GET_MODE (operands[0]) != SImode)
! abort ();
!
! /* Emit an insn that should be matched by the ``sfccsi2'' pattern
! defined below. Use register 32 instead of cc0 since cc0 setter
! and user have to be adjacent. */
! emit_insn (gen_rtx (SET, VOIDmode,
! gen_rtx_REG (CCmode, 32),
! gen_rtx (compare_code, CCmode,
! operands[1],
! operands[2])));
!
! /* Emit conditional branch which checks the calculated value
! of (reg 32) and branches to operands[3] depending on the
! value. */
! emit_jump_insn
! (gen_rtx (SET, VOIDmode, pc_rtx,
! gen_rtx (IF_THEN_ELSE, VOIDmode,
! gen_rtx (NE, CCmode,
! const0_rtx,
! gen_rtx_REG (CCmode, 32)),
! gen_rtx_LABEL_REF (VOIDmode, operands[3]),
! pc_rtx)));
! DONE;
! }"
! )
!
! (define_insn "sfccsi2"
! [(set (reg:CC 32)
! (match_operator:CC 0 "comparison_operator"
! [(match_operand:SI 1 "register_operand" "r,r")
! (match_operand:SI 2 "general_operand" "r,I")]))]
! ""
! "@
! l.sf%C0 \\t%1, %2
! l.sf%C0i \\t%1, %2"
! [(set_attr "type" "logic,logic")
! (set_attr "length" "1,1")]
)
! (define_insn "bf"
! [(set (pc)
! (if_then_else (ne:CC (const_int 0) (reg:CC 32))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "l.bf \\t%0%("
! [(set_attr "type" "branch")
! (set_attr "length" "1")]
)
! (define_insn "bnf"
! [(set (pc)
! (if_then_else (eq:CC (const_int 0) (reg:CC 32))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "l.bnf \\t%0%("
! [(set_attr "type" "branch")
! (set_attr "length" "1")]
)
;;
;; Moves
;;
--- 122,333 ----
;;
! ;; Conditional Branches & Moves
;;
! (define_expand "cmpsi"
! [(match_operand:SI 0 "register_operand" "r,r")
! (match_operand:SI 1 "nonmemory_operand" "I,r")]
! ""
! "
! or1k_cmp_op[0] = operands[0];
! or1k_cmp_op[1] = operands[1];
! DONE;
! "
)
! (define_expand "movsicc"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (if_then_else:SI (ne (const_int 0) (reg:BI 0))
! (match_operand:SI 2 "register_operand" "r")
! (match_operand:SI 3 "register_operand" "r")))]
! ""
! "
! if ( GET_CODE(operands[1]) == EQ ) {
! rtx tmp = operands[2];
! operands[2] = operands[3];
! operands[3] = tmp;
! }
! "
)
! (define_expand "beq"
! [(set (reg:BI 0) (eq (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bne"
! [(set (reg:BI 0) (ne (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "blt"
! [(set (reg:BI 0) (lt (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "ble"
! [(set (reg:BI 0) (le (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bgt"
! [(set (reg:BI 0) (gt (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bge"
! [(set (reg:BI 0) (ge (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bltu"
! [(set (reg:BI 0) (ltu (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bleu"
! [(set (reg:BI 0) (leu (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bgtu"
! [(set (reg:BI 0) (gtu (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_expand "bgeu"
! [(set (reg:BI 0) (geu (match_dup 1) (match_dup 2)))
! (set (pc) (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "
! operands[1] = or1k_cmp_op[0];
! operands[2] = or1k_cmp_op[1];
! "
! )
!
! (define_insn "*sfcc"
! [(set (reg:BI 0)
! (match_operator 0 "comparison_operator"
! [(match_operand:SI 1 "register_operand" "r,r")
! (match_operand:SI 2 "nonmemory_operand" "I,r")]))]
! ""
! "@
! l.sf%C0i \\t%1,%2
! l.sf%C0 \\t%1,%2"
! [(set_attr "type" "logic,logic")
! (set_attr "length" "1,1")]
! )
!
! (define_insn "*bf"
! [(set (pc)
! (if_then_else (ne (const_int 0) (reg:BI 0))
! (label_ref (match_operand 0 "" ""))
! (pc)))]
! ""
! "l.bf \\t%l0%("
! [(set_attr "type" "branch")
! (set_attr "length" "1")]
)
+ (define_insn "*bnf"
+ [(set (pc)
+ (if_then_else (eq (const_int 0) (reg:BI 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "l.bnf \\t%l0%("
+ [(set_attr "type" "branch")
+ (set_attr "length" "1")]
+ )
+
+ (define_insn "*cmovf"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (if_then_else:SI (ne (const_int 0) (reg:BI 0))
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "l.cmov \\t%0,%1,%2"
+ [(set_attr "type" "move")
+ (set_attr "length" "1")]
+ )
+
+ (define_insn "*cmovnf"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (if_then_else:SI (eq (const_int 0) (reg:BI 0))
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "l.cmov \\t%0,%2,%1"
+ [(set_attr "type" "move")
+ (set_attr "length" "1")]
+ )
+
;;
;; Moves
;;
***************
*** 397,409 ****
case 0:
return \"l.lhs \\t%0,%1\\t # extendhisi2\";
case 1:
! return \"l.slli \\t%0,%1,16\;l.srai \\t%0,%0,16\\t # extendhisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,shift")
! (set_attr "length" "1,2")])
(define_insn "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
--- 526,538 ----
case 0:
return \"l.lhs \\t%0,%1\\t # extendhisi2\";
case 1:
! return \"l.exths \\t%0,%1\\t # extendhisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,extend")
! (set_attr "length" "1,1")])
(define_insn "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
***************
*** 414,426 ****
case 0:
return \"l.lbs \\t%0,%1\\t # extendqisi2\";
case 1:
! return \"l.slli \\t%0,%1,24\;l.srai \\t%0,%0,24\\t # extendqisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,shift")
! (set_attr "length" "1,2")])
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
--- 543,555 ----
case 0:
return \"l.lbs \\t%0,%1\\t # extendqisi2\";
case 1:
! return \"l.extbs \\t%0,%1\\t # extendqisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,extend")
! (set_attr "length" "1,1")])
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
***************
*** 431,437 ****
case 0:
return \"l.lhz \\t%0,%1\\t # zero_extendhisi2\";
case 1:
! return \"l.andi \\t%0,%1,0xffff\\t # zero_extendhisi2\";
default:
return \"invalid alternative\";
}
--- 560,566 ----
case 0:
return \"l.lhz \\t%0,%1\\t # zero_extendhisi2\";
case 1:
! return \"l.exthz \\t%0,%1\\t # zero_extendhisi2\";
default:
return \"invalid alternative\";
}
***************
*** 448,463 ****
case 0:
return \"l.lbz \\t%0,%1\\t # zero_extendqisi2\";
case 1:
! return \"l.andi \\t%0,%1,0x00ff\\t # zero_extendqisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,logic")
(set_attr "length" "1,1")])
;;
! ;; Shift operations
;;
(define_insn "ashlsi3"
--- 577,592 ----
case 0:
return \"l.lbz \\t%0,%1\\t # zero_extendqisi2\";
case 1:
! return \"l.extbz \\t%0,%1\\t # zero_extendqisi2\";
default:
return \"invalid alternative\";
}
"
! [(set_attr "type" "load,extend")
(set_attr "length" "1,1")])
;;
! ;; Shift/rotate operations
;;
(define_insn "ashlsi3"
***************
*** 514,519 ****
--- 643,666 ----
[(set_attr "type" "shift,shift")
(set_attr "length" "1,1")])
+ (define_insn "rotrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,L")))]
+ ""
+ "*
+ switch(which_alternative) {
+ case 0:
+ return \"l.ror \\t%0,%1,%2\";
+ case 1:
+ return \"l.rori \\t%0,%1,%2\";
+ default:
+ return \"invalid alternative\";
+ }
+ "
+ [(set_attr "type" "shift,shift")
+ (set_attr "length" "1,1")])
+
;;
;; Logical bitwise operations
;;
***************
*** 580,610 ****
[(set_attr "type" "logic")
(set_attr "length" "1")])
- ;; gen_rtx_XOR(Himode ... mising XOR for HImode define_insn
- ;;(define_expand "one_cmplhi2"
- ;; [(set (match_operand:HI 0 "register_operand" "=r")
- ;; (not:HI (match_operand:HI 1 "register_operand" "r")))]
- ;; ""
- ;; "
- ;; {
- ;; if ((reload_in_progress | reload_completed) == 0) {
- ;; rtx tmpreg, tmp;
- ;;
- ;; tmp = gen_rtx(SET, HImode, tmpreg = gen_reg_rtx(HImode),
- ;; GEN_INT(0xffff));
- ;; emit_insn(tmp);
- ;; emit_insn(gen_rtx(SET, HImode, operands[0],
- ;; gen_rtx_XOR(HImode, operands[1], tmpreg)));
- ;; DONE;
- ;; }
- ;; }
- ;; ")
-
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "l.xori \\t%0,%1,-1"
[(set_attr "type" "logic")
(set_attr "length" "1")])
--- 727,737 ----
[(set_attr "type" "logic")
(set_attr "length" "1")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "l.xori \\t%0,%1,0xffff"
[(set_attr "type" "logic")
(set_attr "length" "1")])
***************
*** 646,662 ****
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
""
! "*
! switch(which_alternative)
! {
! case 0:
! return \"l.sub \\t%0,%1,%2\";
! case 1:
! return \"l.addi \\t%0,%1,%n2\";
! default:
! return \"invalid alternative\";
! }
! "
[(set_attr "type" "add,add")
(set_attr "length" "1,1")])
--- 773,781 ----
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
""
! "@
! l.sub \t%0,%1,%2
! l.addi \t%0,%1,%n2"
[(set_attr "type" "add,add")
(set_attr "length" "1,1")])
***************
*** 691,697 ****
--- 810,818 ----
[(set_attr "type" "mul")
(set_attr "length" "1")])
+ ;;
;; jumps
+ ;;
(define_insn "jump"
[(set (pc)
***************
*** 707,745 ****
"l.jr \\t%0%("
[(set_attr "type" "jump")
(set_attr "length" "1")])
-
- ;;
- ;; Output insns for conditional branches; RTL for these is
- ;; generated in gen_cond_branch().
- ;;
-
- ; (define_insn "branch_output"
- ; [(set (pc) (if_then_else (eq (const_int 0)
- ; (cc0))
- ; (label_ref (match_operand 0 "" "")) (pc)))]
- ; ""
- ; "l.bnf \\t%0%("
- ; [(set_attr "type" "branch")
- ; (set_attr "length" "1")])
-
- ; (define_insn "branch_output_rev"
- ; [(set (pc) (if_then_else (ne (const_int 0)
- ; (cc0))
- ; (label_ref (match_operand 0 "" "")) (pc)))]
- ; ""
- ; "l.bf \\t%0%("
- ; [(set_attr "type" "branch")
- ; (set_attr "length" "1")])
-
-
- ;;(define_insn "set_output2"
- ;; [(set (cc0)
- ;; (match_operator:SI 0 "comparison_operator"
- ;; [(match_operand:SI 1 "register_operand" "r")
- ;; (match_operand:SI 2 "immediate_operand" "I")]))]
- ;; ""
- ;; "l.sf%C0i \\t%1,%2"
- ;; [(set_attr "type" "compare")])
;;
;; Calls
--- 828,833 ----
|
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