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From: verno@a...<verno@a...>
Date: Fri Jul 30 17:18:36 CEST 2004
Subject: [openrisc] onchip_ram problem
Dear All,

When I make my Soc I followed the HW tutorial instruction I made the
onchip_ram_top.v and then generate the onchip_ram with the coregenerator. When
I add to the hierarchy the onchip_ram block searches for BLKMEMSP_V5_0
module. I foundt the BLKMEMSP_V5_0.v file in an ise library and add to the
hierarchy. After I try to translate the Soc or the onchip_ram_top or onchip_ram the
translation is failed with NgdBuild error 406.

I try to generate another ram module in the Soc project as a new IP(CoreGen...) it
succed and I could translate it, but when I look the schematic I found that on the
onchip_ram_top the onchip_ram modules address and data wires aren't conected
to the onchip_ram_top address and data wires. We looked the onchip_ram_top
which is in the HW tutorial and haven't found problem on it. So my question is that
have anybody found a same problem or how can I solve this problem?

Thank you!
Regardes,
Erno Varga