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----- Original Message -----

Dear Damjan,
Thank you your help, the jp1 server works, there was a problem with the
jtag negated reset and the jtag module. The next step is the hello word 
implementation, I checked and correct the hello.c, board.h, and ram.ld 
like the SW tutorial. board.h and ram.ld there are some differences 
because on my SoC there are IC and DC and the onchip ram is smaller 
(2k) than the example. I make the hello.or32 and start the gdb, but 
when I write the following instruction:target jtag  jtag://localhost:9999
I get an error message: Unable to set flags for JTAG proxy socket 5 to 
value 0x401d79c0 I don't know what cause these problem, I think it's 
free from the hello word c files, maybe the gdb installation is wrong but I 
followed the toolchain instructins (I use Mandrake Linux)?

I have to start the jp1 server before run the gdb or not?

Thank yuo your kindness!
Best regards!
Erno Varga

----- Original Message ----- 
From: Damjan Lampret<damjanl@o...> 
To: 
Date: Tue Jul 27 04:22:54 CEST 2004 
Subject: [openrisc] jp1 server 

> ----- Original Message ----- 
> From: <verno@a...> 
> To: <openrisc@o...> 
> Sent: Monday, July 26, 2004 6:09 PM 
> Subject: Re: [openrisc] jp1 server 
> > Dear Damjan, 
> > Thank you your quick anwser. I have read the hardware and 
> software 
> tutorial and 
> > followed the directions, but unfortunately the jp1 server 
> couldn't 
> communicate with 
> > the SoC. I read the the jp1.c file and found that in xilinx 
> mode it isn't 
> use the 
> > trst_pad_i, but on the dbg_top.v there is a trst signal. I put 
> the trst 
> signal to switch 
> > which is on the board and before I use the jp1 software push 
> the reset 
> button is it 
> > good method or not? 
> Yes it should be OK. 
> > The ISE write: the application could work up to 50MHz, so I 
> just put the 
> clk signal 
> > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk 
> is the same 
> > in my SoC. I'm not use the ibufg modul (if I use the ISE write 
> an error 
> ngdbuild 
> > 466 ) and not use the CLKDLL. 
> > On the HW tutorial there is an instruction remove 
> .genpc_stop_prefetch 
> > (genpc_stop_prefetch) the line from the or1200_cpu.v, the 
> newest ORP there 
> isn't 
> > a line like this .genpc_stop_prefetch (1'b0) is it good or I 
> have to 
> remove it? 
> You can ignore this. There used to be unused port definition 
> genpc_stop_prefetch and some synthesis tools had problems with 
> unsused 
> ports. It is no longer there so don't worry about it. 
> > I measured the jtag module signals with an oscilloscope and 
> sometimes the 
> clk 
> > signal isn't go to the 3,3V peak just approximateli 1,7V is it 
> a normal or 
> my jtag 
> > module isn't work properly? 
> It is rather low. Check your datasheet for the FPGA what is the 
> lowest VIH 
> level for clock input. BTW make sure your clock inputs of SOC are 
> using 
> clock inputs of FPGA. 
> regards, 
> Damjan 
> > 
> > Thank you your anwser! 
> > 
> > Best regards 
> > Erno Varga 
> > 
> > 
> > 
> > ----- Original Message ----- 
> > From: Damjan Lampret<damjanl@o...> 
> > To: 
> > Date: Fri Jul 23 17:35:31 CEST 2004 
> > Subject: [openrisc] jp1 server 
> > 
> > > > If I use just some modules (or1k,debug unit, uart, 
> cop matrix) 
> > > the jp1 
> > > server could 
> > > > communicate the Soc? 
> > > Yes or1k and debug are enough to connect jp1 / gdb. 
> > > There are two versions of debug, one that works with jp1 
> and one 
> > > that works 
> > > with jp2. Make sure you use the right one. The tutorial 
> is for jp1 
> > > (but the 
> > > concept is the same for jp2) 
> > > 
> http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf 
> > > 
> http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf 
> > > regards, 
> > > Damjan 
> > > 
> > > 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/openrisc 
> > 
> 
> 