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From: Javier Castillo<jcastillo@e...>
Date: Tue Jul 27 11:05:45 CEST 2004
Subject: [openrisc] Bug in nc.scr file in orp/orp_soc
Hello:

I found a little bug in orp_soc simulation scripts.
To simulate OpenRisc platform with ncverilog you have to add in file nc.src
file the following line in the uart16550 sources section:

../../rtl/verilog/uart16550/uart_sync_flops.v

Regards

Javier Castillo