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Message
From: psungil@n...<psungil@n...>
Date: Tue Jul 6 03:12:23 CEST 2004
Subject: [openrisc]I have a problem.
Hi~ All.
I have a problem at openrisc synthesis.
It's not make a bit file withe xilinx ISE 6.1i.
look at a below.
It's a report of Xilinx.
Number of Block RAMs: 57 out of 28 203% (OVERMAPPED)
please, tell me about how to make a fit in FPGA's area.
below~!!
---------------------------------------------------------------
Release 6.1i Map G.26
Xilinx Mapping Report File for Design 'xsv_fpga_top'
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv800-hq240-
4 -cm
area -pr b -k 4 -c 100 -tx off -o xsv_fpga_top_map.ncd
xsv_fpga_top.ngd
xsv_fpga_top.pcf
Target Device : xv800
Target Package : hq240
Target Speed : -4
Mapper Version : virtex -- $Revision: 1.16 $
Mapped Date : Tue Jul 06 09:05:45 2004
Design Summary
--------------
Number of errors: 1
Number of warnings: 31
Logic Utilization:
Total Number Slice Registers: 4,756 out of 18,816 25%
Number used as Flip Flops: 4,724
Number used as Latches: 32
Number of 4 input LUTs: 11,426 out of 18,816 60%
Logic Distribution:
Number of occupied Slices: 7,682 out of 9,408 81%
Number of Slices containing only related logic: 7,682 out of 7,682
100%
Number of Slices containing unrelated logic: 0 out of 7,682
0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number 4 input LUTs: 12,730 out of 18,816 67%
Number used as logic: 11,426
Number used as a route-thru: 248
Number used for Dual Port RAMs: 1,056
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs: 152 out of 166 91%
IOB Flip Flops: 94
Number of Tbufs: 576 out of 9,632 5%
Number of Block RAMs: 57 out of 28 203% (OVERMAPPED)
Number of GCLKs: 3 out of 4 75%
Number of GCLKIOBs: 3 out of 4 75%
Total equivalent gate count for design: 1,129,206
Additional JTAG gate count for IOBs: 7,440
Peak Memory Usage: 193 MB
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