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Hi,

Hi,
cores list might get you more replies then here.
regards,
Damjan

----- Original Message ----- 
From: "Daniel Wiklund" <danwi@i...>
To: <openrisc@o...>
Sent: Tuesday, June 29, 2004 3:03 PM
Subject: [openrisc] Wishbone incremental burst write

> Hi,
> 
> I know this is slightly off-topic for this forum but I couldn't find any
> other forum that was extremely much better suited for this question...
> 
> I have a Wishbone slave where I would like to support both Wishbone
> classic and incremental burst type cycles. I have full confidence in the
> specification for classic read and write as well as incremental burst
> read. The thing I'm a bit puzzled by is incremental burst write... Is
> such a thing even possible with the constraints given in the Wishbone
> standard? 
> 
> A master that wishes to write using incremental burst must assert the
> CTI signals accordingly but the slave can completely ignore this and
> execute the classic cycles. The problem occur when considering data
> transport between master and slave for a write. The master has to
> present the data in advance (i.e. before ack of last data) so that the
> slave can use the incremental address feature. But the master must
> expect classic style writes as well, forcing the data to be constant
> until an ack is received. This is very inconsistent ;) Are there any
> other opinions/interpretations than this one out there?
> 
> The text that's getting me a bit confused is Rule 4.40 in the Wishbone
> standard stating that the master must use "the same operation (either
> read or write)" for the entire incremental address burst, implying that
> write operations are possible...
> 
> // Daniel Wiklund
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