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Message
From: Matjaz Breskvar<phoenix@o...>
Date: Tue Jun 29 10:28:33 CEST 2004
Subject: [openrisc] Architecture simulation of basic.S
* gurumurt@c... (gurumurt@c...) wrote:
> Now Iam getting the following error, when I run or32-uclinux-sim, even
> before I reach the sim> prompt:
>
>
> Section: .reset, vaddr: 0x04000000, paddr: 0x04000000, offset:
> 0x00004000, size: 0x000001a0
> EXCEPTION: write out of memory (32-bit access to 04000000)
> Exception 0x200 (Bus Error) at 0x0, EA: 0x0, ppc: 0x0, npc: 0x0, #0
> EXCEPTION: write out of memory (32-bit access to 04000004)
> Exception 0x200 (Bus Error) at 0x0, EA: 0x0, ppc: 0x0, npc: 0x0, #0
> EXCEPTION: write out of memory (32-bit access to 04000008)
> Exception 0x200 (Bus Error) at 0x0, EA: 0x0, ppc: 0x0, npc: 0x0, #0
> ....
> .....
> EXCEPTION: write out of memory (32-bit access to 04000c90)
> Exception 0x200 (Bus Error) at 0x0, EA: 0x0, ppc: 0x0, npc: 0x0, #0
>
> In the orp.ld file flash is configured to start at 0x4000000. Hence my
> program is not loaded on to the flash memory. What could be the
> reason for this?
> Here is my orp.ld file .
the problem is that there is nothing at 0x04000000 address. You'll have to
add a device to sim.cfg or change the location of 'flash'. For a quick
try, you may just change '> flash' into '> ram' and see if simulation goes
through.
> ***********************************************************************************
> MEMORY
> {
> vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
> flash : ORIGIN = 0x04000000, LENGTH = 0x00200000
> ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
> icm : ORIGIN = 0x00800000, LENGTH = 0x00004000
> }
>
> SECTIONS
> {
> .reset :
> {
> *(.reset)
> } > flash
>
> .text ALIGN(0x04):
> {
> *(.text)
> } > flash
>
> .rodata :
> {
> *(.rodata)
> } > flash
>
> .dummy ALIGN(0x04):
> {
> _src_beg = .;
> } > flash
>
> .vectors :
> AT ( ADDR (.dummy) )
> {
> _vec_start = .;
> *(.vectors)
> _vec_end = .;
> } > vectors
>
> .icm :
> AT ( ADDR (.dummy) + SIZEOF (.vectors) )
> {
> _icm_start = .;
> *(.icm)
> _icm_end = .;
> } > icm
>
> .data :
> AT ( ADDR (.dummy) + SIZEOF (.vectors) + SIZEOF(.icm) )
> {
> _dst_beg = .;
> *(.data)
> _dst_end = .;
> } > ram
>
> .bss :
> {
> *(.bss)
> } > ram
>
> .stack ALIGN(8192):
> {
> *(.stack)
> FILL(0);
> . = ALIGN(8192);
> _src_addr = .;
> } > ram
>
>
>
> }
>
>
> ***********************************************************************************
>
> Thanks,
> Sankar
> ----- Original Message -----
> From: Matjaz Breskvar<phoenix@o...>
> To:
> Date: Wed Jun 23 23:55:10 CEST 2004
> Subject: [openrisc] Architecture simulation of basic.S
>
> > * gurumurt@c... (gurumurt@c...) wrote:
> > > I changed the orp.ld file's. Now the stack section looks like
> > this:
> > aligning to just 0x4 woun't work since r1 has value 0x1, aligning
> > it will
> > just make it 0x4, but you need more space for stack. let's try this
> > way
> > > .stack ALIGN(8192);
> > > {
> > > *(.stack)
> > FILL(0);
> > . = ALIGN(8192);
> > > _src_addr = .;
> > > } > ram
> > this should make some space on stack... now please check
> > that somewhere value of symbol '_src_addr' gets loaded to r1
> > l.movhi r1,hi(_src_addr)
> > l.ori r1,r1,lo(_src_addr)
> > > But the problem still occurs. I am using the basic.S program
> > from the
> > if you still get 0x600 exception then either aligning didn't work,
> > program
> > doesn't load _src_addr into r1 or it gets corrupted in the first
> > place.
> > just trace the execution and make sure that r1 gets the proper
> > value
> > at the first place and than look where it changes...
> > > or1k/orp/orp_soc/sw/basic package without changing anything.
> > Is the
> > > expected value for r1 at statement "l.jal _report" 1
> > for that program?
> > to be honest i do not know. it could be just a test for unaligned
> > access or
> > something. if you'll still have problems i'll take a closer look.
> > ok?
> > best regards,
> > p.
> >
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
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