OPENCORES.ORG

Hi all,

Michael
are you sure you are using correct release (ie I suggest the latest rel_28).
Please check that you have in your or1200_sprs.v the following line

 if (rst)
  	sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};

sr[EPH] goes through except_prefix to or1200_genpc.v and makes sure that
first fetch comes from the right address. In your case sr[EPH] has to be 1
at reset and this should mean that first fetch would have to come from
0xF000_0000 as indicated by or1200_genpc.v lines:

if (rst)
 	pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P :
`OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;

regards,
Damjan

----- Original Message ----- 
From: "Michael Unnebäck" <michael@h...>
To: "List about OpenRISC project" <openrisc@o...>
Sent: Wednesday, June 23, 2004 11:55 PM
Subject: [openrisc] start of execution

> Hi all,
>
> I have a system with RAM at location 0x00000000 and FLASH memory at
> 0xF0000000.
> In FLASH I have my boot code at adress 0xF0000100. I want OR1200 to
> start execute
> at that adress.
>
> To do so I use the following define in or1200_defines.v
> // Default Exception Prefix
> //
> // 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
> // 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
> //
> `define OR1200_SR_EPH_DEF    1'b1
>
> What happens is the following:
> the first instruction is fetched from 0x100 (reading an undefined value
> from RAM)
> the second instruction is fetched from 0xF0000100
>
> System does not boot.
>
> If I place l.nop (0x18000000) at adress 0x100 with JTAG debug interface
> system boots OK
> when I press reset. But the startup gets a bit complicated ...
>
> Any suggestion on how to solve the problem ?
> /Michael Unneback
>
>
>
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