OPENCORES.ORG

Hi.

Hi Bill
thanks for sharing very interesting results.
Can you make a small PDF and I'll publish it on opencores (for those people
that always ask how big is the OR1200). You can take any of the OR1200
Success story PDFs as a template.

If there is any reason why not to create such PDF please contact me
privately to discuss. Thanks.

regards,
Damjan

----- Original Message ----- 
From: "Bill Cox" <bill@v...>
To: "List about OpenRISC project" <openrisc@o...>
Sent: Monday, June 14, 2004 5:06 PM
Subject: [openrisc] Area result in ViaMask array

> Hi.
>
> I got permission to post the results I got when mapping the OR1200 into
> our .13u ViaMask fabric.
>
> I used Amplify ASIC with an unattainable required clock, so
> timing-driven was full-on.  We don't yet have characterized .13u timing,
> so I wont report those results.  However, I do expect this design to run
> in the 300Mhz range when we're done.
>
> I used 4K instruction and data caches, and no QMEM (internal physical
> address space memory).
>
> After synthesis, ViaPath mapped the logic into 3208 logic cells.  This
> easily fits into 13 logic tiles, which has a total area of 1.02mm^2.
> However, there is also distributed SRAM in this region.  The various
> register files and the instruction and data caches use a total of 22 of
> the ViaMask fabric's 128 word by 32 bit dual-port SRAMs.  Each logic
> tile has one of these, so the total size of logic plus SRAM was SRAM
> limited, and fits in a total of 1.72mm^2.  Of this area, 9 logic tiles
> worth of logic remains free for use, or about 41%.  With 2K byte caches,
> the entire design plus cache should fit in 14 tiles, or about 1.1mm^2.
>
> Bill
>
> On Mon, 2004-06-14 at 03:49, Bill Cox wrote:
> > Hi.
> >
> > I showed off the OR1200 at the Design Automation Conference last week.
> > I think many people there were quite interested in the OR1200 (which
> > made it a good demo for our stuff).  I also used it in a Structured ASIC
> > tutorial I gave on Thursday, which had 16 people.
> >
> > I used a 4K instruction and data caches, and turned off both MMUs, and
> > QMEM.  There was still a ton of SRAM on the 9x10 ViaMask base available,
> > but I wanted the whole CPU (with memory) to fit in one corner of the
> > array.
> >
> > I'll talk to my boss about giving out more detailed results (area,
> > timing, etc).  A bunch of guys copied down the data they saw on the
> > screen, so I think the info is already in the hands of our competitors.
> >
> > While I'm not much of an HDL designer, I was impressed by the quality of
> > the code in the OR1200.  I had very little difficulty using it.  Thanks
> > to the authors for making it available.
> >
> > Bill
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/openrisc
>
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