|
Message
From: meleth_esp@y...<meleth_esp@y...>
Date: Fri May 21 19:18:18 CEST 2004
Subject: [openrisc] Problem with Register File modelsim simulation
Hello: In a previous post I comment that I develop a simple testbench that
executes a load instruction, but when the data bus is going to assert
strobe lines all the signal from the bus going to X.
I found the reason. The simulation only works with the register file
with the OR1200_RFRAM_GENERIC selected. With OR1200_RFRAM_DUALPORT or
OR1200_RFRAM_TWOPORT selected and the FPGA target memories in generic
mode the simulation makes the previous commented.
I dont know if it is the desirable behaviour, Is it?
Regards
|
Browse
