LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Johan Rydberg<jrydberg@g...>
    Date: Fri May 14 14:46:38 CEST 2004
    Subject: [openrisc] 1 bit condition code register
    Top

    On Sat, 15 May 2004, Damjan Lampret wrote:

    : Actually, I was doing a lot of analysis in 1999 looking at the Alpha model
    : and comparing it to the traditional model of flags. If you remember at the
    : time I defined only one true flag and that is "F" flag; the one set by sfXX
    : instructions. Everything else like CY came later and these are not real
    : flags... The alpha model doesn't have much advantage.

    I do not have any problems at all with having a single -flag- register.
    But I wouldn't miss a "set register if flag is set" instruction, or
    simply a copy-flag-to-gpr instruction. This would not break the
    current ISA, but could be seen as an extension. Maybe something to
    think about for the next revision?

    Hope you're feeling better, Damjan.

    ~j


     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.