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Message
From: Michael Scott<mike.scott@j...>
Date: Wed May 5 12:40:20 CEST 2004
Subject: [openrisc] QMEM Generic single-port synchronous RAM model
Hi,
Is there a bug in the Generic single-port synchronous RAM model for qmem
(file : or1200_spram_2048x32_bw.v) ?
Looking at code below, I can't see how the cpu can write more than 1 byte at
a time
32/16 bit writes only update mem_0 due to the inferred priority encoder
always @(posedge clk)
if (ce && !we) begin
do_reg[7:0] <= #1 mem_0[addr];
do_reg[15:8] <= #1 mem_1[addr];
do_reg[23:16] <= #1 mem_2[addr];
do_reg[31:24] <= #1 mem_3[addr];
end
else if (ce && we[0])
mem_0[addr] <= #1 di[7:0];
else if (ce && we[1])
mem_1[addr] <= #1 di[15:8];
else if (ce && we[2])
mem_2[addr] <= #1 di[23:16];
else if (ce && we[3])
mem_3[addr] <= #1 di[31:24];
should the code be structured as:
always @(posedge clk)
if (ce && ~|we) begin
do_reg[7:0] <= mem_0[addr];
do_reg[15:8] <= mem_1[addr];
do_reg[23:16] <= mem_2[addr];
do_reg[31:24] <= mem_3[addr];
end
else
begin
if (ce && we[0]) mem_0[addr] <= di[7:0];
if (ce && we[1]) mem_1[addr] <= di[15:8];
if (ce && we[2]) mem_2[addr] <= di[23:16];
if (ce && we[3]) mem_3[addr] <= di[31:24];
end
Regards,
Mike Scott
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