OPENCORES.ORG

Hi

Quoting or1200_defines.v 
// If you plan to run WB:RISC clock fixed to 1:1, disable 
// both defines 

In general however I'd recommend you to enable
OR1200_CLKDIV_2_SUPPORTED

and disable (comment out)
OR1200_CLKDIV_4_SUPPORTED

and set clmode_i port to 2'b00.

regards
Damjan

----- Original Message ----- 
From: <kevinlinsun@h...>
To: <openrisc@o...>
Sent: Tuesday, May 04, 2004 7:09 PM
Subject: Re: [openrisc] Is there something wrong when WB:RISC clock = 1:1?

> Hi
>     Thanks for your reply.
>     but i just want to make WB:RISC clock = 1:1.how should i do?
> 
> best regards, 
> kevin
>  
> ----- Original Message ----- 
> From: Damjan Lampret<lampret@o...> 
> To: 
> Date: Mon May  3 11:59:14 CEST 2004 
> Subject: [openrisc] Is there something wrong when WB:RISC clock = 
> 1:1? 
> 
> > Kevin 
> > 
> > you first have to learn to read the comments in front of defines. 
> > or1200_defines.v says: 
> > // 
> > // Clock ratio RISC clock versus WB clock 
> > // 
> > // If you plan to run WB:RISC clock fixed to 1:1, disable 
> > // both defines 
> > // 
> > // For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED 
> > // and use clmode to set ratio 
> > // 
> > // For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use 
> > // clmode to set ratio 
> > `define OR1200_CLKDIV_2_SUPPORTED 
> > //`define OR1200_CLKDIV_4_SUPPORTED 
> > Conclusion: for 1:4 you need to enable both defines. Why are you 
> > commenting 
> > out OR1200_CLKDIV_2_SUPPORTED?? 
> > regards, 
> > Damjan 
> > ----- Original Message ----- 
> > From: <kevinlinsun@h...> 
> > To: <openrisc@o...> 
> > Sent: Tuesday, April 20, 2004 6:00 AM 
> > Subject: [openrisc] Is there something wrong when WB:RISC clock = 
> > 1:1? 
> > > Hi 
> > > When i comment "`define OR1200_CLKDIV_2_SUPPORTED" 
> > > and "`define OR1200_CLKDIV_4_SUPPORTED" or set 
> > clmode_i = 2'b00, 
> > > the system seems to be in a wrong state.Who can tell me how to 
> > make 
> > > WB:RISC clock = 1:1? 
> > > 
> > > best regards, 
> > > kevin 
> > > _______________________________________________ 
> > > http://www.opencores.org/mailman/listinfo/openrisc 
> > > 
> > 
> > 
> _______________________________________________
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> 