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Message
From: Junhu_Wang<Junhu_Wang@s...>
Date: Tue Apr 6 02:43:08 CEST 2004
Subject: =?gb2312?B?tPC4tDogW29wZW5yaXNjXSBBcnRpc2FuIFJhbXMgYW5kIFN5bnRoZXNpcw==?=
You can go to cvs general ram and download memory interface like general_dpram.v
which interface to different vendor for port map and some interface struction. May be can
resolve your problem.
Junhu_Wang/SMIC
-----ÔʼÓʼþ-----
·¢¼þÈË: stony.d.yakovac@e...
[mailto:stony.d.yakovac@e...]
·¢ËÍʱ¼ä: 2004Äê4ÔÂ6ÈÕ 1:46
ÊÕ¼þÈË: openrisc@o...
Ö÷Ìâ: [openrisc] Artisan Rams and Synthesis
I am attempting to do an evaluation synthesis of the OR1200. I have the
Artisan ram generators and the standard cell library for .13G. I am
generating the rams with the attached Makefile of my own creation. I am
getting netlist errors however concerning the OEN pin/s among others. Is
there a standard generation script I do not know about? A standard anything
to help me here? Do I have to manually wrap the Artisan rams? Has anyone
done this before? It seems like a lot of grepping and hand modifications to
get this to work. I can't imagine that someone hasn't eased this process
along a little. Can someone help me?
Makefile:
all: art_hsdp_32x32.v art_hssp_1024x32.v art_hssp_1024x32_bw.v
art_hssp_1024x8.v art_hssp_2048x32.v art_hssp_2048x32_bw.v art_hssp_2048x8.v
art_hssp_256x21.v art_hssp_512x20.v art_hssp_64x14.v art_hssp_64x22.v
art_hssp_64x24.v
art_hsdp_32x32.v:
echo art_hsdp_32x32
rf2sh verilog synopsys primetime postscript -instname art_hsdp_32x32
-words 32 -bits 32 -frequency 200 -ring_width 2 -mux 4 -drive 4 -write_mask
off -wp_size 8 -top_layer met8 -power_type rings -horiz met3 -vert met3
-cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename
"VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname
off -diodes on -inside_ring_type GND
art_hssp_1024x32.v:
echo art_hssp_1024x32
ra1sh verilog synopsys primetime postscript -instname
art_hssp_1024x32 -words 1024 -bits 32 -frequency 200 -ring_width 2 -mux 16
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_1024x32_bw.v:
echo art_hssp_1024x32_bw
ra1sh verilog synopsys primetime postscript -instname
art_hssp_1024x32_bw -words 1024 -bits 32 -frequency 200 -ring_width 2 -mux
16 -drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings
-horiz met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim
"]" -pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case
upper -check_instname off -diodes on -inside_ring_type GND
art_hssp_1024x8.v:
echo art_hssp_1024x8
ra1sh verilog synopsys primetime postscript -instname
art_hssp_1024x8 -words 1024 -bits 8 -frequency 200 -ring_width 2 -mux 8
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met3 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_2048x32.v:
echo art_hssp_2048x32
ra1sh verilog synopsys primetime postscript -instname
art_hssp_2048x32 -words 2048 -bits 32 -frequency 200 -ring_width 2 -mux 8
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met3 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_2048x32_bw.v:
echo art_hssp_2048x32_bw
ra1sh verilog synopsys primetime postscript -instname
art_hssp_2048x32_bw -words 2048 -bits 32 -frequency 200 -ring_width 2 -mux 8
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_2048x8.v:
echo art_hssp_2048x8
ra1sh verilog synopsys primetime postscript -instname
art_hssp_2048x8 -words 2048 -bits 8 -frequency 200 -ring_width 2 -mux 16
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_256x21.v:
echo art_hssp_256x21
rf1sh verilog synopsys primetime postscript -instname
art_hssp_256x21 -words 256 -bits 21 -frequency 200 -ring_width 2 -mux 4
-drive 4 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met3 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_512x20.v:
echo art_hssp_512x20
ra1sh verilog synopsys primetime postscript -instname
art_hssp_512x20 -words 512 -bits 20 -frequency 200 -ring_width 2 -mux 16
-drive 6 -write_mask off -wp_size 8 -top_layer met8 -power_type rings -horiz
met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]"
-pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper
-check_instname off -diodes on -inside_ring_type GND
art_hssp_64x14.v:
echo art_hssp_64x14
rf1sh verilog synopsys primetime postscript -instname art_hssp_64x14
-words 64 -bits 14 -frequency 200 -ring_width 2 -mux 4 -drive 4 -write_mask
off -wp_size 8 -top_layer met8 -power_type rings -horiz met3 -vert met3
-cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename
"VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname
off -diodes on -inside_ring_type GND
art_hssp_64x22.v:
echo art_hssp_64x22
rf1sh verilog synopsys primetime postscript -instname art_hssp_64x22
-words 64 -bits 22 -frequency 200 -ring_width 2 -mux 4 -drive 4 -write_mask
off -wp_size 8 -top_layer met8 -power_type rings -horiz met3 -vert met3
-cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename
"VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname
off -diodes on -inside_ring_type GND
art_hssp_64x24.v:
echo art_hssp_64x24
rf1sh verilog synopsys primetime postscript -instname art_hssp_64x24
-words 64 -bits 24 -frequency 200 -ring_width 2 -mux 4 -drive 4 -write_mask
off -wp_size 8 -top_layer met8 -power_type rings -horiz met3 -vert met3
-cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename
"VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname
off -diodes on -inside_ring_type GND
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