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Message
From: Johan Rydberg<jrydberg@n...>
Date: Tue Mar 16 15:11:37 CET 2004
Subject: [openrisc] [PATCH] GCC: split sfCC+bX
Matjaz Breskvar <phoenix@o...> wrote:: and about the codesize. the biggest (all?) reduction is because of l.sfCCi
: usage. if compare is to 16 bit value, there is no need to load that into
: register and then compare.
Also the l.sfCC insns can be scheduled into a delay slot.
I'll see if I can backport a change to the 3.2.3 version that would probably
decrease the code size a bit.
Currently loads is done in the following way;
l.movhi r3,hi(sym)
l.ori r3,r3,lo(sym)
l.lwz r3,0(r3)
I've splitted up the l.movhi/l.ori insn (it is considered one insn by GCC)
into two separate, making two things possible:
1) they can be scheduleded independent of each other. for example,
the l.ori insn can be put in a delay slot.
2) with a small fix to binutils (libbfd) you can generate the following
code for a load:
l.movhi r3,hi(sym)
l.lwz r3,lo(sym)(r3)
same can be done for stores. the reason for the fix in bfd is that
"l.ori" does not sign extend it's immediate, which lwz/addi/sw does.
if the displacement is negative the high bits of l.movhi must be
adjusted. otherwise an invalid address will get calculated.
Do you think this would effect code size at all? It only eliminates one
insn.
--
Johan Rydberg, Free Software Developer, Sweden
http://rtmk.sf.net | http://www.nongnu.org/guss/
Playing Grovskopa - B1 - Strap-on Suncica (Version
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