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Message
From: Ben A. Abderazek<ben@s...>
Date: Wed Feb 11 08:21:53 CET 2004
Subject: [openrisc] "W" register in RISC( processor
Hello,
I downloaded the verilog source code of the RISC 8 processor from the CVS
page.
I have a question about the "W" register.
As indicated bellow, the "dbus" (the output of the ALU) data is written into
this register. This register is used later as one of the input for the ALU.
My question is why the output should go first to "W" register and then to
the MUX which is connected to the ALU.
Is it possble to not use the W register at all and connect directly the
"sbus" to the MUX.
=============================
// W Register
always @(posedge clk) begin
if (reset) begin
w <= 8'h00;
end
else begin
if (wwe) begin
w <= dbus;
end
end
end
===========================
Thank you for your help,
/Ben
UEC, IS
www.uec.ac.jp
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