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Message
From: cicadahz@s...<cicadahz@s...>
Date: Tue Dec 16 02:28:46 CET 2003
Subject: [openrisc] I can synthesize the OR1200 with synplify and XilinxISE
hi, Thanks very much for your reply!the problem are as follows: or1200_spram_64x14.v(277): Reference to undefined module
RAMB4_S36
@E:"e:\synplify_prj\openrisc\verilog\or1200_spram_64x14.v":277:10:277:
21
@E: or1200_spram_64x22.v(277): Reference to undefined module
RAMB4_S16
@E:"e:\synplify_prj\openrisc\verilog\or1200_spram_64x22.v":277:10:277:
21
and the following are the source codes that have the problem.
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({unconnected, di[13:0]}),
.EN(ce),
.WE(we),
.DO({unconnected, do[13:0]})
);
I choose the altera device, but the problems are still there. It looks very
strange.
Thanks very much!
----- Original Message -----
From: "Robert Cragie" <rcc@j... >
To: "List about OpenRISC cores,free microprocessors"
<openrisc@o... >
Date: Mon, 15 Dec 2003 18:09:22 -0000
Subject: RE: [openrisc] I can synthesize the OR1200 with synplify
and XilinxISE
>
>
> You will have to give much more information about the problems you
> are
> seeing if you expect to get any help.
>
> Robert Cragie, Design Engineer
>
_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: +44 (0) 114 281 2655111
>
_____________________________________________________________
__
>
> > -----Original Message-----
> > From: openrisc-bounces@o...
> > [mailto:openrisc-bounces@o... ]On Behalf Of
> cicadahz@s...
> > Sent: 15 December 2003 14:24
> > To: openrisc@o...
> > Subject: [openrisc] I can synthesize the OR1200 with synplify
> and Xilinx
> > ISE
> >
> >
> > I download OR1200 core and try to synthesize it with synplify
> and Xilinx
> > ISE, but there are always some problems there. Can anybody
> help me.
> > THanks very much!
> >
> >
>
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