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Message
From: Damjan Lampret<lampret@o...>
Date: Thu Dec 11 21:39:53 CET 2003
Subject: [openrisc] Width of wishbone on OR1200
Hey !It's 32 bits wide. regards,
Damjan
----- Original Message -----
From: "Brian Korsedal" <BKorsedal@b...>
To: "List about OpenRISC cores,free microprocessors"
<openrisc@o...>
Sent: Friday, December 12, 2003 6:32 PM
Subject: [openrisc] Width of wishbone on OR1200
> Hi,
>
> I'm writing a core to interface with an OR1200 processor inside an FPGA.
> I was wondering what is the data width on the wishbone bus? Is it 8,16
> or 32 bits wide?
>
> Thanks,
>
> Brian
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
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