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From: Brian Korsedal<BKorsedal@b...>
Date: Fri Dec 12 18:32:44 CET 2003
Subject: [openrisc] Width of wishbone on OR1200
Hi,

I'm writing a core to interface with an OR1200 processor inside an FPGA.
I was wondering what is the data width on the wishbone bus? Is it 8,16
or 32 bits wide?

Thanks,

Brian

Follow up	Author
[openrisc] Width of wishbone on OR1200	Damjan Lampret