Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: Ben A. Abderazek<ben@s...>
Date: Wed Dec 10 06:04:48 CET 2003
Subject: [openrisc] Branch Target Buffer Hardware Implementation
Hello,

Does any one has some documents ( Verilog or VHDL code is also fine) about a
detailed Branch Target Buffer hardware implementation?

I know that a BTB entry may consist of : branch tag, prediction information,
the branch target address, and instructions at the branch target. But, how
about call and return instructions? Do they have also to be in the BTB ? If
so, how do the fetch unit make difference between a call, return or branch
instructions.

Thank you for your help.

PN: I have seen most of the papers published about BTB, but I did not find a
detailed implementation.

/Ben
IS, UEC