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Message
From: "James A. Morrison" <ja2morri@c...>
Date: Sun, 02 Nov 2003 16:17:55 -0500
Subject: [openrisc] Vector half-word elements mutliply add signed saturated description
Hi,
In the description of lv.madds.h it says that each intermediate
result is added to the corresponding signed half-word of VMAC.
However, in the 64-bit implementation description is has VMAC
being made up of 2 64 bit registers which get filled in 32 bits
at a time. So is VMAC made up of word (32 bit) or half-word
(16 bit) elements for this instruction?
Jim
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