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Message
From: "Philip Gutierrez" <philip_gutierrez@y...>
Date: Thu, 30 Oct 2003 21:39:35 -0500
Subject: RE: [openrisc] or1k, ram, rom
I assume you are asking about an OR1200 system in general. I strongly
recommend using the reference design, however, as a starting point.
Answers are embedded.
-----Original Message-----
From: owner-openrisc@o... [mailto:owner-openrisc@o...]
On Behalf Of christian@m...
Sent: Thursday, October 30, 2003 1:50 PM
To: openrisc@o...
Subject: [openrisc] or1k, ram, rom
I have some questions about OR1200 (or OR1000) based-system.
1. Every peripheral (IP cores) is connected through a Wishbone
interface to correctly communicate with the openrisc processor. Is it
true?
[Philip] Yes this is true.
2.
Address Space
0xf000_0000 - 0xffff_ffff Cached 256MB ROM
0xc000_0000 - 0xefff_ffff Cached 768MB Reserved
0xb800_0000 - 0xbfff_ffff Uncached 128MB Reserved for custom devices
0xa600_0000 - 0xb7ff_ffff Uncached 288MB Reserved
0x9c00_0000 - 0x9cff_ffff Uncached 16MB USB Host Controller 0-15
0x9b00_0000 - 0x9bff_ffff Uncached 16MB USB Func Controller 0-15
0x9600_0000 - 0x96ff_ffff Uncached 16MB PWM/Timer/Counter
Controller 0-15
0x9300_0000 - 0x93ff_ffff Uncached 16MB Memory Controller 0-15
0x9200_0000 - 0x92ff_ffff Uncached 16MB Ethernet Controller 0-15
0x9100_0000 - 0x91ff_ffff Uncached 16MB General-Purpose I/O 0-15
0x9000_0000 - 0x90ff_ffff Uncached 16MB UART16550 Controller 0-15
0x4000_0000 - 0x7fff_ffff Uncached 1GB Reserved
0x0000_0000 - 0x3fff_ffff Cached 1GB RAM
By reading some mails in this forum, the or1200 cpu reads, after reset,
the address 0x100 in rom space (in flash area). So, In fact, it has to
read the instructions from 0xf0000100? How is that possible? How the
address can be mapped into flash area? Is there any decoder that i
don't know?
[Philip] Your internal address bus is 32 bits wide and the internal
address decoder maps the memory controller to 0xFxxx region in 32-bit
space. However, your flash ROM may only have 22 address lines (64 Mbit
x 16). These are connected to the lower 22 address lines (actually A[0]
is not used), so the processor will access 0xf0000100 (internal) but the
flash memory (external) will see 0x000100 (22 bits).
3. How the H/W loading instructions? In fact, the BIOS is within the
0xf000000 area. It stores from rom into ram the OS kernel and it starts
the system initialization. It loads the driver... So the devices are
maybe
described in a device table? Therefore, the OS reads it in order to
install the drivers.
My questions resides only about the H/W loading instructions and how
does the system to work correctly.
4. About the SDRAM, mainly the memories (Flash, SDRAM) must be
outside of the FPGA? And the cpu fetches instructions through the
memory controller?
[Philip] In an FPGA implementation the Flash and SRAM would be external
to the FPGA. Yes, the CPU will fetch instructions through the memory
controller.
About SDRAM, the memory access must be through another memory
controller?
[Philip] Sometimes there is a separate SDRAM controller in higher
performance systems. The reason is that you don't want to add the
additional capacitive load from the flash on the address and data bus.
It is difficult enough to drive four DIMMS at 133 MHz.
Who is responsible to manage the memory space in the system?
[Philip] You are. You are free to place your peripherals wherever you
want. Again, I recommend staying with the memory map of the existing
reference design even if you choose to remove unwanted peripherals.
I hope to understand everything now:)
Thank you
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