LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Dries Driessens <ddr@d...>
    Date: Thu, 23 Oct 2003 08:21:25 +0200
    Subject: Re: [openrisc] Quartus & OR1200
    Top

    Dear Christian,
    
    sounds like a pin allocation problem of some sort.
    
    maybe you should check out the quartus help file for some explanation.
    press with your right-mouse button on the error message and press help.
    
    
    What I'm about to say may offend you and seem arrogant of me, therefor 
    I'm apolagize, Christian, but I'm having the impression that you are a 
    FPGA-digital logic beginner. Damjan Lampret (project maintainer of OR) 
    already warned people before that OpenRISC isn't a one-click solution!
    You should really have some experience to implement not only OpenRISC, 
    but any softcore processor. I share his opinion.
    
    Therefor I suggest 2 things:
    1) get a course on FPGA's and verilog/VHDL. If you already did this: try 
    to first build an asynchronous circuit and then a synchronous 
    state-machine. (simulate and also implement it in real life on a FPGA 
    development board and try to blink some leds on it)
    2) Then start with 'easy' softcore processors (Nios and Microblaze), 
    just to get some experience in the softcore based embedded systems...
    
    Best of luck,
    sincerely,
    Dries
    
    
    christian@m... wrote:
    
    > I compiled OR1200 files with Quartus and an error occurs : 374 I/O for 
    > my device FPGA.
    > 
    > In fact, i would like to create my own IP megafunction in order to add it 
    > to my design.  Any information available to do it with Quartus?
    > 
    > Regards
    > 
    > 
    > 
    > .
    > 
    
    
    
    

    ReferenceAuthor
    [openrisc] Quartus & OR1200Christian

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.