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Message
From: "Tomas Jonsson" <toj@s...>
Date: Wed, 22 Oct 2003 23:45:15 +0200
Subject: [openrisc] prefetch problem
I have a problem that the last executed instruction is executed forever. It
happends in the uart_putc() function of orpmon. The uart_putc() has worked
properly for several times but when a tick interrupt happends in the middle
of it the uart_putc() polling loop not work properly. See the instruction
sequence below.
0xbad0 <uart_putc+124>: l.lbz r3,0x0(r5)
0xbad4 <uart_putc+128>: l.andi r3,r3,0x60
...
0xbbd4 <tick_interrupt+52>: l.jr r9
0xbbd8 <tick_interrupt+56>: l.addi r1,r1,0x4
...
0x2180 <_tick+244>: l.mfspr r31,r0,0x40
0x2184 <_tick+248>: l.lwz r31,0x74(r1)
0x2188 <_tick+252>: l.lwz r3,0x78(r1)
0x218c <_tick+256>: l.addi r1,r1,0x80
0x2190 <_tick+260>: l.rfe
0xbad8 <uart_putc+132>: l.sfne r3,r4
0xbadc <uart_putc+136>: l.bf 0xfffffffd
0xbae0 <uart_putc+140>: l.nop 0x0
0xbad0 <uart_putc+124>: l.lbz r3,0x0(r5)
#(is the never ending instruction, 8c650000)
#after this should the following instr had been executed but never did
0xbad4 <uart_putc+128>: l.andi r3,r3,0x60
0xbad8 <uart_putc+132>: l.sfne r3,r4
0xbadc <uart_putc+136>: l.bf 0xfffffffd
0xbae0 <uart_putc+140>: l.nop 0x0
... and so on.
Another strange thing is that the CPU still is doing infinite instruction
fetch accesses to address 0xbadc. They never stops even if the execution of
instructions seems to stop?!
The caches are disabled. I have attached a wave dump.
Please can someone help me?
If you need more information do not hesitate to ask me.
Best regards, Tomas Jonsson
instructionfetchbug.pdf
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