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Message
From: lzg@g...
Date: Wed, 22 Oct 2003 15:26:36 +0200
Subject: Re: [openrisc] OR1200 store instruction bug?
I got the same unexpected result in modelsim.
Here is a part of my testbench:
reg[31:0] mem;
always @(iwb_adr_o)
begin
case(iwb_adr_o)
32'h00000100:mem=32'h9c200002;//l.addi
r1,r0,0x0002
32'h00000104:mem=32'hd4010800;//l.sw 0
(r1),r1 (l.sw not l.sh)
endcase
end
always @(iwb_stb_o)
begin
if(iwb_stb_o)
begin
iwb_ack_i<=#1 1;
iwb_dat_i<=#1 mem;
end
else
begin
iwb_ack_i<=#1 0;
iwb_dat_i<=#1 iwb_dat_i;
end
end
The result is 0x00020002 on dwb_dat_o,and 0000 on dwb_sel_o.
But when I change to:
32'h00000100:mem=32'h9c200010;//l.addi
r1,r0,0x0004
32'h00000104:mem=32'hd4010800;//l.sw 0
(r1),r1
The result is as I expected:
0x00000004 on dwb_dat_o,and 1111 on dwb_sel_o.
The following got wrong result when I changed:
l.addi r1,r0,0x0001
l.addi r1,r0,0x0002
l.addi r1,r0,0x0003
l.addi r1,r0,0x0005
l.addi r1,r0,0x0006
l.addi r1,r0,0x0007
l.addi r1,r0,0x0008
l.addi r1,r0,0x0009
And others got the correct result,such as:
l.addi r1,r0,0x0010
l.addi r1,r0,0x0011
..
l.addi r1,r0,0x1234
..
It made me puzzled.I do not know where I am wrong.
Regards
----- Original Message -----
From: "Damjan Lampret" <lampret@o... >
To: <openrisc@o... >
Date: Wed, 22 Oct 2003 12:52:59 +0200
Subject: Re: [openrisc] OR1200 store instruction bug?
>
>
> Ups yes that explains it. Many RISC architectures today only allow
> aligned
> accesses including or1k. Compiler will always generate aligned
> accesses. You
> (the assembly programmer) should also.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: "Marko Mlinar" <markom@o... >
> To: <openrisc@o... >
> Sent: Wednesday, October 22, 2003 12:02 PM
> Subject: Re: [openrisc] OR1200 store instruction bug?
>
>
> > Note that you are doing word access to unaligned location. It
> depends on
> your
> > memory controller what will actually happen.
> > Usually you would get e.g. 0x02020202, if you byte access to
> one location.
> >
> > Marko
> >
> > On Wednesday 22 October 2003 09:41, lzg@g... wrote:
> > > Hi all,
> > > I had the RTL test of l.sw instruction with Active
> HDL6.1.
> > > But found the output was not as I expect.
> > > The simple asm program is the following.
> > > l.addi r1,r0,0x0001
> > > l.addi r2,r0,0x0002
> > > l.sw 0(r1),r2
> > > and the binary code is
> > > 9c200001
> > > 9c400002
> > > d4011000
> > > I think that waveform shows 0x00000001 on dwb_adr_o,and
> 0x00000002
> > > on dwb_dat_o.
> > > But In fact the waveform shows 0x00000001 on
> dwb_adr_o,and
> > > 0x00020002 on dwb_dat_o(not 0x00000002).
> > > I am puzzled.Is it a bug?l.sh,l.sb have the similar
> question!
> > >
> > > Regards
> >
> >
> >
>
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