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Message
From: Dries Driessens <ddr@d...>
Date: Wed, 17 Sep 2003 14:25:01 +0200
Subject: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
OK, you convinced me. I rest my case.
Thank you for sharing your experience.
Best regards,
Dries
Robert Cragie wrote:
>>Daniel Wiklund wrote:
>>
>>
>>>On Wed, 17 Sep 2003 11:11:47 +0100
>>>"Robert Cragie" <rcc@j...> wrote:
>>>
>>>
>>>
>>>>I agree with Tomas, the JTAG interface for the OR1200 needs to be on a
>>>>separate interface - standard I/O pins will be OK. Even if you could
>>>>include it on the scan chain of the Xilinx device, the existing
>>>>software and interface for the debugger will not work as it is, as I'm
>>>>sure it only expects one device (i.e. the OR1200 itself) on its scan
>>>>chain.
>>>
>>>
>>>I don't think it is a good idea to try to include the OR1200 JTAG
>>>on the same chain as the Xilinx JTAG. The reason for this is that the
>>>Xilinx device wont be accessible through JTAG before the (correct)
>>>configuration has been downloaded. Basically it would make
>>>reconfiguration of the Xilinx device impossible through JTAG.
>>
>>When using FPGAs and you don't mind power-cycling your board, I
>>disagree. FPGAs are SRAM based, so when power-cycling your board, you
>>loose your configuration with the OR1200 JTAG...
>
>
> ...and you'd mess up the scan chain completely if the device loses its
> configuration, and part of the scan chain relies on the configuration. You
> must have a separate JTAG interface for the OpenRISC.
>
> Also. most FPGAs can be configured to boot from external PROMS, which is the
> first thing they do when they power cycle. This is how we are using the
> Xilinx XCV-4000 on the Avnet development card. Note the PROMs are also in
> the same JTAG scan chain as the Xilinx device itself, which is how they are
> programmed from a PC.
>
> Robert
>
>
>
>
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