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Message
From: Dries Driessens <ddr@d...>
Date: Wed, 17 Sep 2003 13:38:46 +0200
Subject: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
Daniel Wiklund wrote:
> On Wed, 17 Sep 2003 11:11:47 +0100
> "Robert Cragie" <rcc@j...> wrote:
>
>
>>I agree with Tomas, the JTAG interface for the OR1200 needs to be on a
>>separate interface - standard I/O pins will be OK. Even if you could
>>include it on the scan chain of the Xilinx device, the existing
>>software and interface for the debugger will not work as it is, as I'm
>>sure it only expects one device (i.e. the OR1200 itself) on its scan
>>chain.
>
>
> I don't think it is a good idea to try to include the OR1200 JTAG
> on the same chain as the Xilinx JTAG. The reason for this is that the
> Xilinx device wont be accessible through JTAG before the (correct)
> configuration has been downloaded. Basically it would make
> reconfiguration of the Xilinx device impossible through JTAG.
When using FPGAs and you don't mind power-cycling your board, I
disagree. FPGAs are SRAM based, so when power-cycling your board, you
loose your configuration with the OR1200 JTAG...
Or not?
> If the JTAG interface would never be used for downloading configurations
> it would probably be ok, though. So, as I see it, there is no other way
> than to use I/O pins for the OR1200 JTAG.
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