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Message
From: Daniel Wiklund <danwi@i...>
Date: Wed, 17 Sep 2003 13:18:50 +0200
Subject: Re: [openrisc] accessing JTAG lines of Xilinx Virtex-II
On Wed, 17 Sep 2003 11:11:47 +0100
"Robert Cragie" <rcc@j...> wrote:
> I agree with Tomas, the JTAG interface for the OR1200 needs to be on a
> separate interface - standard I/O pins will be OK. Even if you could
> include it on the scan chain of the Xilinx device, the existing
> software and interface for the debugger will not work as it is, as I'm
> sure it only expects one device (i.e. the OR1200 itself) on its scan
> chain.
I don't think it is a good idea to try to include the OR1200 JTAG
on the same chain as the Xilinx JTAG. The reason for this is that the
Xilinx device wont be accessible through JTAG before the (correct)
configuration has been downloaded. Basically it would make
reconfiguration of the Xilinx device impossible through JTAG.
If the JTAG interface would never be used for downloading configurations
it would probably be ok, though. So, as I see it, there is no other way
than to use I/O pins for the OR1200 JTAG.
// Daniel
----
Daniel Wiklund, MScEE, Lic Eng
Computer Engineering, ISY
Linköping University Phone:
581 83 Linköping Work +46 13 28 8965
Sweden Home +46 11 701 59
danwi@i... Mobile +46 70 3215698
http://www.da.isy.liu.se/~danwi/
----
Inter spem curamque, timores inter et iras
omnem crede diem tibi diluxisse supremem:
grata superveniet quae non sperabitur hora.
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